MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 104

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

shown in Figure 6-9. If the bus cycle is a read, the data at the fault address should be
written to the images of the data input buffer, instruction input buffer, or both according to
the data fetch (DF) and instruction fetch (IF) bits.
the status register image must be properly set to reflect the read data if the fault occurred
during the read portion of the cycle and the write operation (i.e., setting the most
significant bit of the memory location) must also be performed. These operations are
required because the entire read-modify-write cycle is assumed to have been completed
by software. Once the cycle has been completed by software, the rerun (RR) bit in the
special status word is set to indicate to the processor that it should not rerun the cycle
when the RTE instruction is executed. If the RR bit is set when an RTE instruction
executes, the MC68010 reads all the information from the stack, as usual.
6.3.10 Address Error
An address error exception occurs when the processor attempts to access a word or long-
word operand or an instruction at an odd address. An address error is similar to an
internally generated bus error. The bus cycle is aborted, and the processor ceases current
processing and begins exception processing. The exception processing sequence is the
same as that for a bus error, including the information to be stacked, except that the
vector number refers to the address error vector. Likewise, if an address error occurs
during the exception processing for a bus error, address error, or reset, the processor is
halted.
On the MC68010, the address error exception stacks the same information stacked by a
bus error exception. Therefore, the RTE instruction can be used to continue execution of
the suspended instruction. However, if the RR flag is not set, the fault address is used
when the cycle is retried, and another address error exception occurs. Therefore, the user
must be certain that the proper corrections have been made to the stack image and user
registers before attempting to continue the instruction. With proper software handling, the
address error exception handler could emulate word or long-word accesses to odd
addresses if desired.
*
the data output or input buffer images, unless the high-byte transfer (HB) bit is set. This condition occurs if a
MOVEP instruction caused the fault during transfer of bits 8–15 of a word or long word or bits 24–31 of a
long word.
MOTOROLA
RR — Rerun flag; 0=processor rerun (default), 1=software rerun
IF
DF — Data fetch to the data input buffer
RM — Read-modify-write cycle
HB — High-byte transfer from the data output buffer or to the data input buffer
BY — Byte-transfer flag; HB selects the high or low byte of the transfer register. If BY is clear, the transfer is word.
RW
FC — The function code used during the faulted access
*
If the faulted access was a byte operation, the data should be moved from or to the least significant byte of
RR
15
— Instruction fetch to the instruction input buffer
— These bits are reserved for future use by Motorola and will be zero when written by the MC68010.
—
14
*
13
I F
Read/write flag; 0=write, 1=read
M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL
DF
12
Freescale Semiconductor, Inc.
Figure 6-9. Special Status Word Format
RM
11
For More Information On This Product,
HB
10
Go to: www.freescale.com
BY
9
RW
8
7
*
In addition, for read-modify-write cycles,
*
3
2
FC2–FC0
6- 19
0