MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 120

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.4 IMMEDIATE INSTRUCTION EXECUTION TIMES
The numbers of clock periods shown in Table 8-5 include the times to fetch immediate
operands, perform the operations, store the results, and read the next operation. The total
number of clock periods, the number of read cycles, and the number of write cycles are
shown in the previously described format. The number of clock periods, the number of
read cycles, and the number of write cycles, respectively, must be added to those of the
effective address calculation where indicated by a plus sign (+).
In Table 8-5, the following notation applies:
8-4
#
Dn — Data register operand
An — Address register operand
M
— Immediate operand
— Memory operand
ADD/ADDA
AND
CMP/CMPA
DIVS
DIVU
EOR
MULS
MULU
OR
SUB
MULS, MULU — The multiply algorithm requires 38+2n clocks where n is defined as:
DIVS, DIVU — The divide algorithm used by the MC68000 provides less than 10% difference
*** Only available effective address mode is data register direct.
Instruction
** The base time of six clock periods is increased to eight if the effective address mode is
+ Add effective address calculation time.
† Word or long only
* Indicates maximum basic value added to word effective address time
MULU: n = the number of ones in the <ea>
MULS: n=concatenate the <ea> with a zero as the LSB; n is the resultant number of 10
register direct or immediate (effective address time should also be added).
MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL
Table 8-4. Standard Instruction Execution Times
between the best- and worst-case timings.
Freescale Semiconductor, Inc.
or 01 patterns in the 17-bit source; i.e., worst case happens when the source
is $5555.
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Byte, Word
For More Information On This Product,
Long
Long
Long
Long
Long
Long
Size
—
—
—
—
Go to: www.freescale.com
op<ea>, An†
6(1/0)+**
6(1/0)+**
8(1/0)+
6(1/0)+
6(1/0)+
8(1/0)+
—
—
—
—
—
—
—
—
—
—
op<ea>, Dn
158(1/0)+*
140(1/0)+*
70(1/0)+*
70(1/0)+*
6(1/0)+**
6(1/0)+**
6(1/0)+**
6(1/0)+**
4(1/0)***
8(1/0)***
4(1/0)+
4(1/0)+
4(1/0)+
6(1/0)+
4(1/0)+
4(1/0)+
op Dn, <M>
12(1/2)+
12(1/2)+
12(1/2)+
12(1/2)+
12(1/2)+
8(1/1)+
8(1/1)+
8(1/1)+
8(1/1)+
8(1/1)+
—
—
—
—
—
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