MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 32

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Address Bus (A23–A0)
MC68008 Address Bus
3.2
This bidirectional, three-state bus is the general-purpose data path. It is 16 bits wide in the
all the processors except the MC68008 which is 8 bits wide. The bus can transfer and
accept data of either word or byte length. During an interrupt acknowledge cycle, the
external device supplies the vector number on data lines D7–D0. The MC68EC000 and
MC68HC001 use D7–D0 in 8-bit mode, and D15–D8 are undefined.
3.3
Address Strobe (
Read/Write (R/
Upper And Lower Data Strobes (
3-4
This 24-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data.
This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles and breakpoint cycles. During interrupt acknowledge cycles,
address lines A1, A2, and A3 provide the level number of the interrupt being
acknowledged, and address lines A23–A4 and A0 are driven to logic high. In 16-Bit
mode, A0 is always driven high.
The unidirectional, three-state buses in the two versions of the MC68008 differ from
each other and from the other processor bus only in the number of address lines and
the addressing range. The 20-bit address (A19–A0) of the 48-pin version provides a 1-
Mbyte address space; the 52-pin version supports a 22-bit address (A21–A0), extending
the address space to 4 Mbytes. During an interrupt acknowledge cycle, the interrupt
level number is placed on lines A1, A2, and A3. Lines A0 and A4 through the most
significant address line are driven to logic high.
Asynchronous data transfers are controlled by the following signals: address strobe,
read/write, upper and lower data strobes, and data transfer acknowledge. These signals
are described in the following paragraphs.
This three-state signal indicates that the information on the address bus is a valid
address.
This three-state signal defines the data bus transfer as a read or write cycle. The R/W
signal relates to the data strobe signals described in the following paragraphs.
These three-state signals and R/W control the flow of data on the data bus. Table 3-1
lists the combinations of these signals and the corresponding data on the bus. When
the R/W line is high, the processor reads from the data bus. When the R/W line is low,
the processor drives the data bus. In 8-bit mode, UDS is always forced high and the
LDS signal is used.
DATA BUS (D15–D0; MC68008: D7–D0)
ASYNCHRONOUS BUS CONTROL
W
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M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
AS
).
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
UDS
,
LDS
).
MOTOROLA