MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 47

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 5
16-BIT BUS OPERATION
The following paragraphs describe control signal and bus operation for 16-bit bus
operations during data transfer operations, bus arbitration, bus error and halt conditions,
and reset operation. The 16-bit bus operation devices are the MC68000, MC68HC000,
MC68010, and the MC68HC001 and MC68EC000 in 16-bit mode. The MC68HC001 and
MC68EC000 select 16-bit mode by pulling mode high or leave it floating during reset.
5.1 DATA TRANSFER OPERATIONS
Transfer of data between devices involves the following signals:
The address and data buses are separate parallel buses used to transfer data using an
asynchronous bus structure. In all cases, the bus master must deskew all signals it issues
at both the start and end of a bus cycle. In addition, the bus master must deskew the
acknowledge and data signals from the slave device.
The following paragraphs describe the read, write, read-modify-write, and CPU space
cycles. The indivisible read-modify-write cycle implements interlocked multiprocessor
communications. A CPU space cycle is a special processor cycle.
5.1.1 Read Cycle
During a read cycle, the processor receives either one or two bytes of data from the
memory or from a peripheral device. If the instruction specifies a word or long-word
operation, the MC68000, MC68HC000, MC68HC001, MC68EC000, or MC68010
processor reads both upper and lower bytes simultaneously by asserting both upper and
lower data strobes. When the instruction specifies byte operation, the processor uses the
internal A0 bit to determine which byte to read and issues the appropriate data strobe.
When A0 equals zero, the upper data strobe is issued; when A0 equals one, the lower
data strobe is issued. When the data is received, the processor internally positions the
byte appropriately.
The word read-cycle flowchart is shown in Figure 5-1 and the byte read-cycle flowchart is
shown in Figure 5-2. The read and write cycle timing is shown in Figure 5-3 and the word
and byte read-cycle timing diagram is shown in Figure 5-4.
MOTOROLA
1. Address bus A1 through highest numbered address line
2. Data bus D0 through D15
3. Control signals
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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