MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 55

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

STATE 12
STATE 13
STATE 14
STATE 15
STATE 16 At the rising edge of S16, the processor asserts U D S or L D S . The
STATE 17
STATE 18
STATE 19
5.1.4 CPU Space Cycle
A CPU space cycle, indicated when the function codes are all high, is a special processor
cycle. Bits A16–A19 of the address bus identify eight types of CPU space cycles. Only the
interrupt acknowledge cycle, in which A16–A19 are high, applies to all the
microprocessors described in this manual. The MC68010 defines an additional type of
CPU space cycle, the breakpoint acknowledge cycle, in which A16–A19 are all low. Other
configurations of A16–A19 are reserved by Motorola to define other types of CPU cycles
used in other M68000 Family microprocessors. Figure 5-10 shows the encoding of CPU
space addresses.
MOTOROLA
ACKNOWLEDGE
ACKNOWLEDGE
(MC68010 only)
BREAKPOINT
INTERRUPT
FC2–FC0, the address bus lines, AS, and R/W remain unaltered.
(refer to Appendix B M6800 Peripheral Interface). If neither termination
The write portion of the cycle starts in S12. The valid function codes on
During S13, no bus signals are altered.
On the rising edge of S14, the processor drives R/W low.
During S15, the data bus is driven out of the high-impedance state as the
data to be written are placed on the bus.
processor waits for DTACK or BERR or VPA, an M6800 peripheral signal.
When VPA is asserted during S16, the cycle becomes a peripheral cycle
signal is asserted before the falling edge at the close of S16, the processor
inserts wait states (full clock cycles) until either DTACK or BERR is asserted.
During S17, no bus signals are altered.
During S18, no bus signals are altered.
On the falling edge of the clock entering S19, the processor negates AS,
UDS, and LDS. As the clock rises at the end of S19, the processor
places the address and data buses in the high-impedance state, and drives
R/W high. The device negates DTACK or BERR at this time.
FUNCTION
2
1
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
1
CODE
1
1
Figure 5-10. CPU Space Address Encoding
1
0
1
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For More Information On This Product,
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31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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23
ADDRESS BUS
CPU SPACE
TYPE FIELD
19
16
3
LEVEL
1 0
0
1
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