MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 56

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The interrupt acknowledge cycle places the level of the interrupt being acknowledged on
address bits A3–A1 and drives all other address lines high. The interrupt acknowledge
cycle reads a vector number when the interrupting device places a vector number on the
data bus and asserts DTACK to acknowledge the cycle.
The timing diagram for an interrupt acknowledge cycle is shown in Figure 5-11.
Alternately, the interrupt acknowledge cycle can be autovectored. The interrupt
acknowledge cycle is the same, except the interrupting device asserts VPA instead of
DTACK. For an autovectored interrupt, the vector number used is $18 plus the interrupt
level. This is generated internally by the microprocessor when VPA (or AVEC) is asserted
on an interrupt acknowledge cycle. DTACK and V P A (A V E C) should never be
simultaneously asserted.
5-10
IPL2–IPL0
*
FC2–FC0
IPL2–IPL0 SAMPLED
IPL2–IPL0 TRANSITION
Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not
recognize anything on data lines D8 through D15 at this time.
IPL2–IPL0 VALID INTERNALLY
D15–D8
A23–A4
DTACK
D7–D0
A3–A1
UDS
LDS
R/W
CLK
AS
*
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 w
Figure 5-11. Interrupt Acknowledge Cycle Timing Diagram
LAST BUS CYCLE OF INSTRUCTION
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
(READ OR WRITE)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
STACK
(SSP)
PCL
(VECTOR NUMBER
ACQUISITION)
IACK CYCLE
w
w
STACK AND
VECTOR
FETCH
w S5 S6
MOTOROLA