MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 79

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MC68HC000RC12

Manufacturer Part Number
MC68HC000RC12
Description
IC MPU 32BIT 12MHZ 68-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68HC000RC12

Processor Type
M680x0 32-Bit
Speed
12MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
16/32Bit
Frequency (max)
12MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
68
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Freescale Semiconductor, Inc.
ADDR
AS
R/W
UDS/LDS
DATA
DTACK
Figure 5-32. Fully Asynchronous Write Cycle
In the asynchronous mode, the accessed device operates independently of the frequency
and phase of the system clock. For example, the MC68681 dual universal asynchronous
receiver/transmitter (DUART) does not require any clock-related information from the bus
master during a bus transfer. Asynchronous devices are designed to operate correctly
with processors at any clock frequency when relevant timing requirements are observed.
A device can use a clock at the same frequency as the system clock (e.g., 8, 10, or 12.5,
16, and 20MHz), but without a defined phase relationship to the system clock. This mode
of operation is pseudo-asynchronous; it increases performance by observing timing
parameters related to the system clock frequency without being completely synchronous
with that clock. A memory array designed to operate with a particular frequency processor
but not driven by the processor clock is a common example of a pseudo-asynchronous
device.
The designer of a fully asynchronous system can make no assumptions about address
setup time, which could be used to improve performance. With the system clock frequency
known, the slave device can be designed to decode the address bus before recognizing
an address strobe. Parameter #11 (refer to Section 10 Electrical Characteristics)
specifies the minimum time before address strobe during which the address is valid.
In a pseudo-asynchronous system, timing specifications allow DTACK to be asserted for a
read cycle before the data from a slave device is valid. The length of time that DTACK
may precede data is specified as parameter #31. This parameter must be met to ensure
the validity of the data latched into the processor. No maximum time is specified from the
assertion of AS to the assertion of DTACK. During this unlimited time, the processor
inserts wait cycles in one-clock-period increments until DTACK is recognized. Figure 5-33
shows the important timing parameters for a pseudo-asynchronous read cycle.
MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
5- 33
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