MC68HC000CRC8 Freescale Semiconductor, MC68HC000CRC8 Datasheet - Page 50

• Manufacturer Part Number: MC68HC000CRC8
• Description: IC MPU 32BIT 8MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000CRC8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

A bus cycle consists of eight states. The various signals are asserted during specific
states of a read cycle, as follows:
STATE 0
STATE 1
STATE 2
STATE 3
STATE 4
STATE 5
STATE 6
STATE 7
5.1.2 Write Cycle
During a write cycle, the processor sends bytes of data to the memory or peripheral
device. If the instruction specifies a word operation, the processor issues both UDS and
LDS and writes both bytes. When the instruction specifies a byte operation, the processor
uses the internal A0 bit to determine which byte to write and issues the appropriate data
strobe. When the A0 bit equals zero, UDS is asserted; when the A0 bit equals one, LDS is
asserted.
5-4
The read cycle starts in state 0 (S0). The processor places valid function
codes on FC0–FC2 and drives R/W high to identify a read cycle.
Entering state 1 (S1), the processor drives a valid address on the address
bus.
On the rising edge of state 2 (S2), the processor asserts AS and UDS, LDS,
or DS.
During state 4 (S4), the processor waits for a cycle termination signal
(DTACK or BERR) or VPA, an M6800 peripheral signal. When VPA is
asserted during S4, the cycle becomes a peripheral cycle (refer to
Appendix B M6800 Peripheral Interface). If neither termination signal is
asserted before the falling edge at the end of S4, the processor inserts wait
states (full clock cycles) until either DTACK or BERR is asserted.
On the falling edge of the clock entering state 7 (S7), the processor latches
data from the addressed device and negates AS, U D S, and LDS. At
the rising edge of S7, the processor places the address bus in the high-
impedance state. The device negates DTACK or BERR at this time.
During an active bus cycle, VPA and BERR are sampled on
every falling edge of the clock beginning with S4, and data is
latched on the falling edge of S6 during a read cycle. The bus
cycle terminates in S7, except when BERR is asserted in the
absence of DTACK. In that case, the bus cycle terminates one
clock cycle later in S9.
During state 3 (S3), no bus signals are altered.
During state 5 (S5), no bus signals are altered.
During state 6 (S6), data from the device is driven onto the data bus.
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
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