MC68HC000RC16 Freescale Semiconductor, MC68HC000RC16 Datasheet - Page 152

• Manufacturer Part Number: MC68HC000RC16
• Description: IC MPU 32BIT 16MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

*These specifications represent improvement over previously published specifications for the 8-, 10-, and 12.5-MHz
** This frequency applies only to MC68HC000 and MC68HC001.
NOTES:
10-12
48
48
Num
58A
MC68000 and are valid only for product bearing date codes of 8827 and later.
57A
47
49
56
58
50
51
53
54
55
57
2,3,5
2
,
5
9
4
7
3
7
1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum
2. Actual value depends on clock period.
3. If #47 is satisfied for both DTACK and BERR , #48 may be ignored. In the absence of DTACK , BERR is an
4. For power-up, the MC68000 must be held in the reset state for 100 ms to allow stabilization of on-chip
5. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data
6. When AS and R/W are equally loaded ( 20;pc), subtract 5 ns from the values given in these columns.
7. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before
8. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may
9. The falling edge of S6 triggers both the negation of the strobes ( AS and DS ) and the falling edge of E. Either
10. 245 ns for the MC68008.
11. 50 ns for the MC68008
12. 50 ns for the MC68008.
Asynchronous Input Setup
Time
BERR Asserted to DTACK
Asserted
DTACK Asserted to BERR
Asserted (MC68010 Only)
AS, DS, Negated to E Low
E Width High
E Width Low
Data-Out Hold from Clock
High
R/ W Asserted to Data Bus
Impedance Change
HALT ( RESET Pulse Width
BGACK Negated to AS, DS ,
R/ W Driven
BGACK Negated to FC, VMA
Driven
BR Negated to AS , DS, R/ W
Driven
BR Negated to FC, AS Driven
E Low to Data-Out Invalid
columns.
asynchronous input using the asynchronous input setup time (#47).
circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the
processor.
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time
(#27) for the following clock cycle.
asserting BGACK.
be reasserted.
of these events can occur first, depending upon the loading on each signal. Specification #49 indicates the
absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of E.
Characteristic
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
Min
450
700
-70
1.5
1.5
10
20
30
30
10
—
0
1
1
8 MHz*
Go to: www.freescale.com
Max
—
—
80
70
—
—
—
—
—
—
—
—
—
—
Min
550
350
-55
1.5
1.5
10
20
20
20
10
—
10 MHz*
0
1
1
Max
—
—
55
55
—
—
—
—
—
—
—
—
—
—
12.5 MHz*
Min
280
440
-45
1.5
1.5
10
20
15
10
10
—
0
1
1
Max
—
—
35
45
—
—
—
—
—
—
—
—
—
—
16.67 MHz
Min
220
340
-35
1.5
1.5
10
10
10
10
—
0
0
1
1
12F
Max
—
—
—
35
—
—
—
—
—
—
—
—
—
—
Min
220
340
-35
1.5
1.5
10
10
10
—
5
0
0
1
1
16 MHz
Max
—
35
—
—
—
—
—
—
—
—
—
—
—
—
MOTOROLA
Min
–30
190
290
1.5
1.5
10
10
20 MHz
—
5
0
5
0
1
1
Max
—
—
—
30
—
—
—
—
—
—
—
—
—
—
••
Unit
clks
clks
clks
clks
clks
ns
ns
ns
ns
ns
ns
ns
ns
ns