MC68HC000RC16 Freescale Semiconductor, MC68HC000RC16 Datasheet - Page 62

no-image

MC68HC000RC16

Manufacturer Part Number
MC68HC000RC16
Description
IC MPU 32BIT 16MHZ 68-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC000RC16

Processor Type
M680x0 32-Bit
Speed
16MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC000RC16
Manufacturer:
TI
Quantity:
6 000
Part Number:
MC68HC000RC16
Manufacturer:
CY
Quantity:
1 520
Bus arbitration control is implemented with a finite-state machine. State diagram (a) in
Figure 5-18 applies to all processors using 3-wire bus arbitration and state diagram (b)
applies to processors using 2-wire bus arbitration, in which BGACK is permanently
negated internally or externally. The same finite-state machine is used, but it is effectively
a two-state machine because BGACK is always negated.
In Figure 5-18, input signals R and A are the internally synchronized versions of BR and
BGACK. The BG output is shown as G, and the internal three-state control signal is shown
as T. If T is true, the address, data, and control buses are placed in the high-impedance
state when AS is negated. All signals are shown in positive logic (active high), regardless
of their true active voltage level. State changes (valid outputs) occur on the next rising
edge of the clock after the internal signal is valid.
A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in
Figure 5-19. The bus arbitration timing while the bus is inactive (e.g., the processor is
performing internal operations for a multiply instruction) is shown in Figure 5-20.
When a bus request is made after the MPU has begun a bus cycle and before AS has
been asserted (S0), the special sequence shown in Figure 5-21 applies. Instead of being
asserted on the next rising edge of clock, BG is delayed until the second rising edge
following its internal assertion.
5-16
Figure 5-17. External Asynchronous Signal Synchronization
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
INTERNAL SIGNAL VALID
EXTERNAL SIGNAL SAMPLED
BR (EXTERNAL)
BR (iNTERNAL)
Freescale Semiconductor, Inc.
For More Information On This Product,
CLK
Go to: www.freescale.com
47
MOTOROLA

Related parts for MC68HC000RC16