MPC8349EZUAJDB Freescale Semiconductor, MPC8349EZUAJDB Datasheet

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... To locate published errata or updates for this document, refer to the MPC8349EA product summary page on our website, as listed on the back cover of this document, or contact your local Freescale sales office. © 2006–2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8349EAEC Rev. 12, 10/2010 Contents 1 ...

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... Figure 1 shows the major functional e300 Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Cache Cache 64/32b PCI Controller PCI1 0/32b PCI Controller PCI2 DMA Controller DMA TSEC MII, GMII, TBI, RTBI, RGMII 10/100/1Gb TSEC MII, GMII, TBI, RTBI, RGMII 10/100/1Gb Freescale Semiconductor ...

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... PCI agent mode on PCI1 interface — PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses and support for delayed read transactions — Posting of processor-to-PCI and PCI-to-memory writes MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Overview 3 ...

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... Buffer size of 256 bytes for each execution unit, with flow control for large data sizes • Universal serial bus (USB) dual role controller — USB on-the-go mode with both device and host functionality MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Four groups of interrupts with programmable priority — External and internal interrupts directed to host processor — Redirects interrupts to external INTA pin in core disable mode. — Unique vector number for each interrupt source MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Overview 5 ...

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... I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev interfaces 2 C-1 EPROM by boot sequencer embedded Freescale Semiconductor ...

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... IN REF 6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol ...

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... Recommended Unit Value 1.3 V ± 1.2 V ± 1.3 V ± 1.2 V ± 2.5 V ± 125 mV V 1.8 V ± 3.3 V ± 330 mV V 2.5 V ± 125 mV 3.3 V ± 330 mV V 2.5 V ± 125 mV 3.3 V ± 330 /OV / Freescale Semiconductor Notes — — — — ...

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... To minimize the time that I/O pins are actively driven recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor 11 ns (Min) +7 ...

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... Table 5. = 105°C, and a Dhrystone benchmark J target, and I 105°C, and 105°C, and a Dhrystone benchmark J = 105°C, and an J Freescale Semiconductor Unit ...

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... MHz, 32 bits 66 MHz, 32 bits 50 MHz, 32 bits TSEC I/O MII load = 25 pF GMII or TBI RGMII or RTBI USB 12 MHz 480 MHz Other I/O — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor (1.8 V) (2.5 V) (3.3 V) (3.3 V) 0.31 0.42 — ...

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... KHK CLKIN — — Min Max 2 0 –0.3 0 — ± — ± — ±50 IN Table 7 provides the clock input Typical Max Unit — 66 MHz — — ns 1.0 2.3 ns — — ±150 ps Freescale Semiconductor Unit V V μA μA μA Notes 1, 6 — ...

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... Table 9. RESET Pins DC Electrical Characteristics Parameter Input high voltage Input low voltage Input current 2 Output high voltage Output low voltage MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV DD Symbol Min t — G125 t — ...

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... MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev (continued) Symbol Condition Min 3 not relevant for those pins. OH Min 512 — 1 Max Unit — 0.4 V Max Unit Notes — PCI_SYNC_IN — CLKIN — PCI_SYNC_IN — PCI_SYNC_IN — PCI_SYNC_IN — CLKIN — PCI_SYNC_IN — ns — — PCI_SYNC_IN Freescale Semiconductor ...

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... Input high voltage Input low voltage Output leakage current Output high current (V = 1.420 V) OUT MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Table 11. PLL and DLL Lock Times Min — 7680 Section 19, “Clocking.” (typ) = 2.5 V and DDR2 SDRAM is GV ...

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... OUT DD (typ) = 1.8 V (continued) DD — (typ Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT (typ Max Unit 2.625 V 0.51 × 0.04 V REF – 0.18 V REF μA –9.9 — mA — Freescale Semiconductor — Notes 1 1 Notes — — 4 — — ...

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... AC timing specifications for the DDR SDRAM when GV Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions with GV Parameter AC input low voltage AC input high voltage MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor (typ Symbol C IO ...

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... T is the clock period and abs (t CISKEW t MCK DISKEW Figure 4. DDR Input Timing Diagram Max Unit ps 600 750 750 750 . This can be DISKEW ) is the absolute CISKEW timing parameter. DISKEW t DISKEW Freescale Semiconductor Notes — — — ...

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... MHz 266 MHz 200 MHz MDQ/MECC/MDM output hold with respect to MDQS 400 MHz 333 MHz 266 MHz 200 MHz MDQS preamble start MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor of (1.8 or 2.5 V) ± 5 Symbol Min t DDKHAS 1.95 2.40 3 ...

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... DDKHMHmax DDKHMH(min) = –0.6 ns Figure 5. Timing Diagram for t Min Max Unit –0.6 0.6 ns memory clock reference (K) goes MCK describes the DDR timing (DD) from the DDKHMH can be modified through control of the DDKHMH follows the DDKHMP DDKHMH Freescale Semiconductor Notes 6 for inputs DDKHAS ). DDKHMH ...

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... DC electrical characteristics for the DUART interface of the MPC8349EA. Table 21. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current (0.8 V ≤ V ≤ MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor t MCK t ,t DDKHAS DDKHCS t ,t ...

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... Symbol V V Table 22. DUART AC Timing Specifications Parameter th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are Min Max OV – 0.2 — — 0.2 OL Value Unit 256 baud > 1,000,000 baud 16 — Section 8.3, Freescale Semiconductor Unit V V Notes — ...

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... The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII Timing Specifications This section describes the GMII transmit and receive AC timing specifications. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor 24. The RGMII and RTBI signals in Symbol Conditions 2 LV — ...

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... Figure 8. GMII Transmit AC Timing Diagram Min Typ Max — 8.0 — 43.75 — 56.25 0.5 — 5.0 — — 1.0 — — 1.0 — 8.0 — 45 — 55 for inputs and symbolizes GMII transmit timing (GT) GTKHDV clock GTX t GTXR Freescale Semiconductor Unit ...

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... GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 9 shows the GMII receive AC timing diagram. G RX_CLK RXD[7:0] RX_DV RX_ER MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor /OV of 3.3 V ± 10 Symbol t GRX t ...

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... For example MTX t t MTXF MTXH t MTKHDX Figure 10. MII Transmit AC Timing Diagram Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 for inputs symbolizes MII transmit timing MTKHDX t MTXR Freescale Semiconductor Unit MTX ...

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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 11 provides the AC test load for TSEC. Output Figure 12 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor /OV of 3.3 V ± 10 Symbol t MRX t MRX t ...

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... Min Typ Max — 8.0 — 40 — 60 1.0 — 5.0 — — 1.0 — — 1.0 — 8.0 — 45 — 55 symbolizes the TBI transmit TTKHDV (K) going high (H) until TTX represents the TBI (T) transmit TTX t TTXR t TTKHDX Freescale Semiconductor Unit for inputs ...

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... Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0. Figure 14 shows the TBI receive AC timing diagram. PMA_RX_CLK1 RCG[9:0] PMA_RX_CLK0 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor /OV of 3.3 V ± 10 Symbol t ...

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... RGTH RGT RGTH RGT t RGTR t RGTF 6 t G12 t /t G125H G125 Min Typ Max Unit –0.5 — 0.5 1.0 — 2.8 7.2 8.0 8 — — 0.75 — — 0.75 — 8.0 — 47 — the lowest speed transitioned. RGT Freescale Semiconductor ...

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... MDIO and MDC are provided in Table 32. MII Management DC Electrical Characteristics Powered at 2.5 V Parameter Supply voltage (2.5 V) Output high voltage Output low voltage Input high voltage Input low voltage MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] ...

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... Table 2. Typ Max Unit Notes 2.5 — MHz 400 — ns — — ns — 170 ns — — ns — — ns — Freescale Semiconductor Unit μA μA Unit μA μA 2 — — 3 — — — ...

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... Figure 16 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 16. MII Management Interface Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor is 3.3 V ± 10% or 2.5 V ± 5 Symbol Min t — MDHF (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... OV – 0.2 — DD — 0.2 Min Max Unit 15 — — — ns — — ns for inputs symbolizes USB timing (US) for USIXKH symbolizes USKHOX of the signal in question for 3 Freescale Semiconductor Unit V V μ Notes 2–5 2–5 2–5 2–5 2–5 ...

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... Table 37. Local Bus DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current = –100 μA High-level output voltage 100 μA Low-level output voltage MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor = 50 Ω Ω Figure 17. USB AC Test Load t USIVKH t t ...

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... Unit Notes 7.5 — 1.5 — 2.2 — 1.0 — 1.0 — 1.5 — — 2.5 — — 4.5 ns — — 4.5 ns — — 4 — 4 — — — 3 for inputs symbolizes local bus timing (LB) LBIXKH1 of the signal in question for 3 Freescale Semiconductor ...

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... DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 19 provides the AC test load for the local bus. Output MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor 1 Symbol t LBK t ...

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... Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev LBIVKH t LBKHOV t LBKHOZ t t LBKHOV LBKHOX t LBKHOZ t t LBKHOV LBKHOX t LBOTOT t LBKHLR t LBIXKH t LBKLOV t t LBKHOZ LBKLOV t t LBKLOV LBOTOT t LBIXKH t LBIXKH t LBIXKH t LBIVKH t LBIVKH Freescale Semiconductor ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 ...

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... Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ t LBKLOV t LBIVKH t t LBKHOZ t LBKLOV t LBIXKH t LBIXKH LBIVKH Freescale Semiconductor ...

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... DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8349EA. Table 40. JTAG Interface DC Electrical Characteristics Parameter Input high voltage Input low voltage Input current Output high voltage MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 ...

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... JTDXKH TMS, TDI t JTIXKH t JTKLDV TDO t JTKLOV t JTKLDX TDO t JTKLOX Min Max — 0.5 — 0.4 Figure 27 through 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 4 — — 10 — — 2 — Freescale Semiconductor Unit V V — — — — ...

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... Figure 27 provides the JTAG clock input timing diagram. JTAG External Clock Figure 27. JTAG Clock Input Timing Diagram Figure 28 provides the TRST timing diagram. TRST MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Table 2). 2 Symbol t JTKLDZ TDO t JTKLOZ (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 29. Boundary-Scan Timing Diagram VM t JTIVKH t JTKLOV t JTKLOZ VM = Midpoint Voltage ( JTDXKH Input Data Valid Output Data Valid VM t JTIXKH Input Data Valid Output Data Valid Freescale Semiconductor ...

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... Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time:CBUS compatible masters bus devices MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor 2 C interface of the MPC8349EA. 2 Table 42 Electrical Characteristics of 3.3 V ± 10%. DD Symbol 0.7 × ...

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... OV V — symbolizes I C timing (I2) with I2DVKH clock reference (K) going to the high (H) I2C symbolizes I I2PVKH (min) of the SCL signal) to bridge the SCL signal. I2CL AC parameter. I2CF Ω I2KHKL I2CF t I2CR t I2PVKH P Freescale Semiconductor Unit ns μs μ for inputs 2 C clock I2C S ...

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... Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock Input hold from clock REQ64 to PORESET setup time MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Table 44. PCI DC Electrical Characteristics Symbol Test Condition ≥ ...

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... PCI timing (PC) with respect to the time hard reset (R) went PCRHFV 1 (continued) Max Unit Notes for inputs symbolizes PCI timing (PC) with PCIVKH , reference (K) going SYS Max Unit Notes — — — — clocks for inputs symbolizes PCI timing (PC) with PCIVKH , reference (K) going SYS Freescale Semiconductor ...

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... TGATE, and RTC_CLK. Table 47. Timer DC Electrical Characteristics Parameter Input high voltage Input low voltage Input current Output high voltage MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor = 50 Ω Figure 33. PCI AC Test Load t PCIVKH Figure 34. PCI Input AC Timing Diagram ...

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... Symbol Condition 8 3 ensure proper operation. TIWID Symbol Condition V — — — – Min Max Unit — 0.5 V — 0 Symbol Min Unit TIWID Min Max Unit 2 0 –0.3 0.8 V μA — ±5 2.4 — V — 0.5 V — 0.4 V Freescale Semiconductor ...

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... IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least t MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor ns to ensure proper operation. PIWID Symbol ...

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... DD –0.3 0.8 — ±5 2.4 — — 0.5 — 0 Min Max — 6 NIKHOV 0.5 — NIKHOX — — — NIIVKH t 0 — NIIXKH 4 — NEIVKH 2 — NEIXKH symbolizes the internal timing NIKHOX Freescale Semiconductor Unit V V μ Unit for inputs ...

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... Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8349EA is available in a tape ball grid array (TBGA). See Section 18.2, “Mechanical Dimensions for the MPC8349EA MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor = 50 Ω Figure 36 ...

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... The package parameters are provided in the following list. The package type × 35 mm, 672 tape ball grid array (TBGA). Package outline Interconnects Pitch Module height (typical) Solder balls Ball diameter (typical) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev × 672 1. Sn/36 Pb/2 Ag (ZU package) 96.5 Sn/3.5Ag (VV package) 0.64 mm Freescale Semiconductor ...

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... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement must exclude any effect of mark on top surface of package. Figure 39. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8349EA TBGA MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Package and Pin Listings 55 ...

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... AC32, AE32, AH31, AL32 AG34 Power Pin Type Notes Supply — DD I/O OV — DD I/O OV — DD I/O OV — — I/O OV — — — DD I/O OV — — — — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD Freescale Semiconductor ...

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... MDQS[0:8] MBA[0:1] MA[0:14] MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] MODT[0:3] MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Package Pin Number AE33 AF32 AE34 AF34 AF33 AG33 AG32 Y32, Y34, AA32 Y31, Y33, AA31 A19 DDR SDRAM Memory Interface ...

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... O GV — DD I/O — 9 I/O — 9 I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — — — — — DD I/O OV — DD I/O OV — — DD I/O OV — I/O OV — — — — — DD I/O OV — DD I/O OV — DD Freescale Semiconductor ...

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... DR_D2_VMO_SE0 MPH1_D3_SPEED/DR_D3_SPEED MPH1_D4_DP/DR_D4_DP MPH1_D5_DM/DR_D5_DM MPH1_D6_SER_RCV/ DR_D6_SER_RCV MPH1_D7_DRVVBUS/ DR_D7_DRVVBUS MPH1_NXT/DR_SESS_VLD_NXT MPH1_DIR_DPPULLUP/ DR_XCVR_SEL_DPPULLUP MPH1_STP_SUSPEND/ DR_STP_SUSPEND MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Package Pin Number B25 D24 A25 B24 A24 D23 B23 A23 F22 E22 USB Port 1 A26 B26 ...

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... DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — DD I/O OV — DD I/O OV — — DD I/O OV — DD I/O OV — — I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — DD1 I DD1 Freescale Semiconductor ...

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... TSEC2_RXD[3:0]/GPIO1[13:16] TSEC2_RX_ER/GPIO1[25] TSEC2_TXD[7]/GPIO1[31] TSEC2_TXD[6]/ DR_XCVR_TERM_SEL TSEC2_TXD[5]/ DR_UTMI_OPMODE1 TSEC2_TXD[4]/ DR_UTMI_OPMODE0 TSEC2_TXD[3:0]/GPIO1[17:20] MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Package Pin Number Gigabit Reference Clock C8 A17 F12 D10 A11 B11 B17 B16, D16, E16, F16 E10, A8, F10, B8 ...

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... E20 F20 Power Pin Type Notes Supply I/O OV — DD I/O LV — DD2 I/O OV — — DD I/O OV — DD I/O OV — DD I/O OV — — I/O OV — DD I/O OV — DD I/O OV — — — — — — — — — — Freescale Semiconductor ...

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... QUIESCE PORESET HRESET SRESET THERM0 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Package Pin Number B20 A20 B19 Test D22 AL13 PMC A18 System Control C18 B18 D18 Thermal Management K32 Power and Ground Signals L31 AP12 V nominal, 1 ...

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... Ethernet management interface I/O (2.5 V, 3.3 V) Power for three LV — DD2 speed Ethernet #2 I/O (2.5 V, 3.3 V) Power for core V — DD (1.2 V nominal, 1.3 V for 667 MHz) PCI, 10/100 OV — DD Ethernet, and other standard (3 DDR — reference voltage Freescale Semiconductor ...

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... No external pull-down resistors are allowed to be attached to this net. 11. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to LV 12. For systems that boot from local bus (GPCM)-controlled NOR flash, a pullup on LGPL4 is required. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Package Pin Number AD2 . ...

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... Div Clock /2 lbiu_clk Unit /n To Local Bus Memory LBIU Controller DLL csb_clk to Rest of the Device PCI Clock Divider Figure 40. MPC8349EA Clock Subsystem 6 DDR MCK[0:5] Memory 6 MCK[0:5] Device LCLK[0:2] Local Bus LSYNC_OUT Memory Device LSYNC_IN PCI_CLK/ PCI_SYNC_IN PCI_SYNC_OUT 8 PCI_CLK_OUT[0:7] Freescale Semiconductor ...

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... TSEC2 Security core USB DR, USB MPH PCI1, PCI2 and DMA complex MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Table 56 specifies which units have a configurable clock frequency. Table 56. Configurable Clock Units Default Frequency csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 ...

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... Table 58 shows the multiplication factor Freescale Semiconductor Unit MHz MHz MHz MHz MHz MHz MHz MHz ...

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... Table 59. CSB Frequency Options for Host Mode CFG_CLKIN_DIV SPMF 1 at Reset Low 0010 Low 0011 Low 0100 Low 0101 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor RCWL[SPMF] System PLL Multiplication Factor 0111 × 7 1000 × 8 1001 × 9 1010 × 10 1011 × 11 1100 × ...

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... Frequency (MHz 33.33 66.67 150 200 175 233 200 266 225 300 250 333 275 300 325 133 100 200 133 266 166 333 200 233 2 25 33.33 66.67 133 100 200 100 133 266 125 166 333 Freescale Semiconductor ...

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... Core VCO frequency = core frequency × VCO divider VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor csb_clk : 16.67 2 Input Clock Ratio ...

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... PLL bypassed (PLL off, csb_clk clocks core directly) 0 1:1 0 1:1 0 1:1 0 1:1 1 1.5:1 1 1.5:1 1 1.5:1 1 1.5:1 0 2:1 0 2:1 0 2:1 0 2:1 1 2.5:1 1 2.5:1 1 2.5:1 1 2.5:1 0 3:1 0 3:1 0 3:1 0 3:1 1 VCO Divider PLL bypassed (PLL off, csb_clk clocks core directly Freescale Semiconductor ...

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... MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Table 62. Suggested PLL Configurations 533 MHz Device Input CSB Core CSB Clock Freq Freq Freq Freq (MHz) (MHz) ...

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... Core CSB Clock Freq Freq Freq (MHz) (MHz) 2 (MHz) 66 200 66 266 66 333 Value Unit °C θJA °C θJMA °C θJMA °C θJMA °C θJMA °C θJMA °C/W R 3.8 θJB °C/W R 1.7 θJC Freescale Semiconductor Core Freq (MHz) 600 667 667 Notes ...

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... The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor × where P ...

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... When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance θ JA MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev × θ Ψ determine the junction temperature and a measure of the JT Ψ × θ θ Freescale Semiconductor ...

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... Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor . For instance, the user can change the size of the heat θ CA ...

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... Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev 603-224-9988 408-567-8082 818-842-7277 408-436-8770 800-522-2800 603-635-5102 781-935-4850 800-248-2481 888-642-7674 Freescale Semiconductor ...

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... The platform PLL generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor × θ ...

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... V Figure 41, one to each of the four AV 10 Ω 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 41. PLL Power Supply Filter Circuit respectively). The through (or L2AV ) and LV pin of the and GND Freescale Semiconductor DD pins ...

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... The measured voltage source with an external precision differential termination resistor of value R MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor , required. Unused active high inputs should trimmed until the voltage at the pad equals P ) ÷ ...

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... Solving for the output impedance gives R ÷ source Table 65. Impedance Characteristics PCI Signals PCI Output Clocks (Not Including PCI (Including Output Clocks) PCI_SYNC_OUT) 25 Target 42 Target 25 Target 42 Target NA Table 105°C. j NOTE × (V ÷ source term 1 DDR DRAM Symbol 20 Target Target DIFF Freescale Semiconductor – 1 Unit ...

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... MHz (at 200 MHz CSB). AJF marked parts support DDR1 and DDR2 data rate up to 333 MHz (at a CSB of 333 MHz). Table 67 shows the SVR settings by device and package type. Device MPC8349EA MPC8349A MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Table 66. Part Numbering Nomenclature Temperature 2 Package Range Blank = 0 to 105° ...

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... Table 30, changed V (min Table 8, “EC_GTX_CLK125 AC Timing Specifications.” 57, updated frequency for max csb_clk to 333 MHz and DDR2, from 100-200 to 100-133 66, footnote 1, changed 667(TBGA) to 533(TBGA). footnote 4, added data rate for DDR1 (max) to (20%–80%). IH TBGA, changed solder ball for TBGA Freescale Semiconductor ...

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... PLL supply voltage of 1.3 V for 667-MHz parts. 4 12/2006 Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified T from 900 ps to 775 ps. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor Substantive Change(s) Table 7. Specifications,” clarified that AC table is for ULPI only. 39, corrected t ...

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... Table 55, “MPC8349EA (TBGA) Pinout Listing,” in row AVDD3 changed power supply from “AVDD3” to ‘—.’ 0 3/2006 Initial public release. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Substantive Change(s) + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8. DD and VIL in Table 40Table 44,“PCI DC Electrical IH Freescale Semiconductor ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...