MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Freescale Semiconductor
Technical Data
MPC8533E PowerQUICC III
Integrated Processor
Hardware Specifications
1
This section provides a high-level overview of MPC8533E
features.
the device.
1.1
The following list provides an overview of the device feature
set:
© 2010 Freescale Semiconductor, Inc.
MPC8533E Overview
High-performance, 32-bit core enhanced by
resources for embedded cores defined by the Power
ISA, and built on Power Architecture® technology:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
— Signal-processing engine (SPE) APU (auxiliary
Figure 1
Key Features
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as
they are defined by the SPE APU.
shows the major functional units within
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
11. Programmable Interrupt Controller . . . . . . . . . . . . . .50
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
13. I
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
15. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . .58
17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . .76
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
21. System Design Information . . . . . . . . . . . . . . . . . . .100
22. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . .109
23. Document Revision History . . . . . . . . . . . . . . . . . . . 111
1. MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . .1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . .16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
8. Enhanced Three-Speed Ethernet (eTSEC),
9. Ethernet Management Interface Electrical
Document Number: MPC8533EEC
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Contents
Rev. 5, 01/2011

Related parts for MPC8533EVTARJ

MPC8533EVTARJ Summary of contents

Page 1

... Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. © 2010 Freescale Semiconductor, Inc. Document Number: MPC8533EEC Rev. 5, 01/2011 Contents 1. MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 ...

Page 2

... Three inbound windows plus a configuration window on PCI and PCI Express – Four outbound windows plus default translation for PCI and PCI Express • DDR/DDR2 memory controller — Programmable timing supporting DDR and DDR2 SDRAM — 64-bit data interface MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 3

... RSA and Diffie-Hellman; programmable field size up to 2048 bits – Elliptic curve cryptography with F 511 bits — DEU—Data Encryption Standard execution unit – DES, 3DES MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor m and F(p) modes and programmable field size MPC8533E Overview 3 ...

Page 4

... Up to eight-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. — Two protocol engines available on a per chip select basis: MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev addressing mode 2 C interface Freescale Semiconductor ...

Page 5

... Programmable Ethernet preamble insertion and extraction bytes — MAC address recognition: – Exact match on primary and virtual 48-bit unicast addresses – VRRP and HSRP support for seamless router fail-over – exact-match MAC addresses supported MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor MPC8533E Overview 5 ...

Page 6

... Supports PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 7

... Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download • IEEE Std 1149.1™-compliant, JTAG boundary scan • 783 FC-PBGA package MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor MPC8533E Overview 7 ...

Page 8

... Table 1. Absolute Maximum Ratings Symbol 256-Kbyte L2 Cache 64-Bit e500 DDR/DDR2 Coherency SDRAM Module Controller PCI Express PCI x4/x2/x1 PCI PCI Express x1 DMA x4/x2/x1 1 Max Value Unit –0 –0 –0 –0 Freescale Semiconductor Notes — — — — ...

Page 9

... Characteristic Core supply voltage PLL supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers DDR and DDR2 DRAM I/O voltage MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1 (continued) Symbol Max Value GV –0.3 to 2.75 DD – ...

Page 10

... V ± 125 mV TV 3.3 V ± 165 mV DD 2.5 V ± 125 mV OV 3.3 V ± 165 3.3 V ± 165 2.5 V ± 125 mV 1.8 V ± GND GND REF DD LV GND GND GND GND ° and not necessarily the voltage Freescale Semiconductor Notes — ...

Page 11

... I/O supply voltage. OV appropriate LVCMOS type specifications. The DDR2 SDRAM interface uses a single-ended differential receiver referenced the externally supplied MV the SSTL2 electrical signaling standard. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor + 20 GND Not to Exceed 10% ...

Page 12

... Table 3. Output Drive Capability Programmable Output Impedance (Ω (default) 45 (default) 125 25 42 (default (half strength mode 150 , Supply Notes Voltage 2.5 V — 1.8 V — 2.5/3.3 V — 3.3 V — 3.3 V — required. If there is DD core supply, the I/Os DD Freescale Semiconductor ...

Page 13

... Section 4.3, “eTSEC Gigabit Reference Clock Timing” • Section 4.4, “Platform to FIFO Restrictions” • Section 4.5, “Other Input Clocks” MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 4. Table 4. MPC8533E Core Power Dissipation Platform V DD ...

Page 14

... Table 2. Table 5. Typical Max Unit — 133 MHz — 30.3 ns 1.0 2.1 ns — — ±150 ps and Section 19.3, “e500 Core PLL Ratio,” Table 5 Min Max Unit 20 60 kHz 0 1.0 % Freescale Semiconductor Notes 1 — 2 — for ratio Notes — 1 ...

Page 15

... FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 3.2 For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more than 167 MHz. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor , and minimum clock low time is 2 × t CCB Symbol ...

Page 16

... Table 9. PLL Lock Times Min — — — (typ) = 2.5 V and DDR2 SDRAM Max Unit Notes μs — — — SYSCLKs 1 μs — — — SYSCLKs 1 — SYSCLKs 1 5 SYSCLKs 1 Max Unit Notes μs 100 — μs 50 — μs 50 — (typ Freescale Semiconductor ...

Page 17

... DDR SDRAM component(s) when GV (typ Table 12. DDR SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor . Symbol Min GV 1.71 DD 0.49 × REF ...

Page 18

... Max Unit μA 50 — mA — (typ Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT REF Min Max Unit μA — 500 (typ Max Unit MV – 0.25 V REF + 0.25 — V Freescale Semiconductor Notes 4 — — Notes 1 1 Notes 1 Notes — — ...

Page 19

... Figure CISKEW 3. Maximum DDR1 frequency is 400 MHz. Figure 3 shows the DDR SDRAM input timing diagram. MCK[n] MCK[n] MDQS[n] MDQ[x] Figure 3. DDR SDRAM Input Timing Diagram (t MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol Min V — 0.31 IH REF Symbol ...

Page 20

... MHz 900 t 0.75 x tMCK DDKHMP Max Unit Notes — 7 — — — 7 — — — — — 7 — — — — — 7 — — — — 0 — 7 — — — — — 7 — — — — — Freescale Semiconductor ...

Page 21

... Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t MCK[n] MCK[n] MDQS MDQS MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1 Symbol Min t 0.4 x tMCK DDKHME (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

Page 22

... MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev MCK DDKHAS DDKHCS DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH t DDKHDS DDKHDX = 50 Ω Figure 6. DDR AC Test Load Symbol –2 mA DDKHME t DDKLDS t DDKLDX Ω Min Max Unit 0 –0.3 0.8 V μA — ±5 2.4 — V Freescale Semiconductor Notes — — 1 — ...

Page 23

... Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 9, “Ethernet Management Interface Electrical Characteristics.” MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol = 2 mA) ...

Page 24

... Table 1 and Table 2. Min Max Unit 2.375 2.625 V 2.0 — V — 0.4 V 1.70 — V — 0.7 V μA — ±15 Table 1 and Table 2. Freescale Semiconductor Notes 1, 2 — — — — Notes 1, 2 — — — — ...

Page 25

... Table 24. FIFO Mode Receive AC Timing Specification At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5% Parameter/Condition RX_CLK clock period RX_CLK duty cycle RX_CLK peak-to-peak jitter MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 23 and Table 24. Symbol ...

Page 26

... GTX t GTKHDX t GTXR Typ Max Unit — 0.75 ns — 0.75 ns — — ns — — FITF FITR t FIRR t FIRF Min Typ Max Unit — 8.0 — ns 0.2 — 5.0 ns — — 1.0 ns Freescale Semiconductor Notes — — — — Notes — 2 — ...

Page 27

... RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RX_CLK to RXD[7:0], RX_DV, RX_ER hold time RX_CLK clock rise (20%–80%) MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 1 Symbol t GTXF (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

Page 28

... GMII (G) receive (RX) clock. For rise and fall times, the latter convention = 50 Ω Figure 10. eTSEC AC Test Load t GRX t t GRXF GRXH t GRDXKH t GRDVKH Figure 11. GMII Receive AC Timing Diagram Min Typ Max Unit — — 1.0 ns symbolizes GMII receive GRDVKH clock reference ( Ω GRXR Freescale Semiconductor Notes — for ...

Page 29

... At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%. Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 2.5 V ± Symbol ...

Page 30

... MRX t t MRXH MRXF Valid Data t MRDVKH Figure 14. MII Receive AC Timing Diagram Typ Max Unit — — ns — — ns — 4.0 ns — 4.0 ns symbolizes MII receive MRDVKH clock reference (K) MRX Ω MRXR t MRDXKL Freescale Semiconductor Notes — — — — for ...

Page 31

... TBI receive AC timing specifications. Table 30. TBI Receive AC Timing Specifications At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5%. Parameter/Condition PMA_RX_CLK[0:1] clock period PMA_RX_CLK[0:1] skew MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 1 Symbol Min t — ...

Page 32

... SKTRX t TRXH Figure 16. TBI Receive AC Timing Diagram Typ Max Unit — — — ns — — ns — 2.4 ns — 2.4 ns symbolizes TBI receive TRDVKH clock reference (K) TRX t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Freescale Semiconductor Notes — — — — — for ...

Page 33

... Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period duration Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol Min t 7.5 ...

Page 34

... TBI (T) receive (RX) clock. Note also that the notation for rise RGT t RGTH t SKRGT_TX TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXD[9] TXEN TXERR t RGTH RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT_TX RXD[4] RXD[9] RXDV RXERR Typ Max Unit Notes — 0.75 ns — of the lowest speed transitioned RGT t RGT t SKRGT_RX t RGT t SKRGT_RX Freescale Semiconductor ...

Page 35

... R (rise (fall). Figure 19 shows the RMII transmit AC timing diagram. REF_CLK TXD[1:0] TX_EN TX_ER Figure 19. RMII Transmit AC Timing Diagram MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 33. of 3.3 V ± 2.5 V ± 5 Symbol Min t 15 ...

Page 36

... RMRDV Figure 21. RMII Receive AC Timing Diagram Typ Max Unit 20.0 25 — 250 ps — 2.0 ns — 2.0 ns — — ns — — ns symbolizes MII receive MRDVKH clock reference (K) MRX Ω RMRR t RMRDX Freescale Semiconductor Notes — — — — — — — for ...

Page 37

... MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics “Section 8, “Enhanced Three-Speed Ethernet Table 35. Symbol – ...

Page 38

... For example, t from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. t MDC t t MDCF MDCH t MDDVKH t MDDXKH t MDKHDX Typ Max Unit — symbolizes management MDKHDX t MDCR Freescale Semiconductor Notes — for ...

Page 39

... DC electrical characteristics for the local bus interface operating 1.8 V DC. DD Table 39. Local Bus DC Electrical Characteristics (1.8 V DC) Parameter High-level input voltage Low-level input voltage Input current ( MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol –2 mA mA) ...

Page 40

... LBIXKH1 t 1.0 — LBIXKH2 t 1.5 — LBOTOT t — 2.9 LBKHOV1 t — 2.8 LBKHOV2 t — 2.7 LBKHOV3 t — 2.7 LBKHOV4 t 0.7 — LBKHOX1 t 0.7 — LBKHOX2 t — 2.5 LBKHOZ1 Unit Notes V — V — = 3.3 V. For Unit Notes — — ns — Freescale Semiconductor ...

Page 41

... Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor DD 1 Symbol t LBKHOZ2 (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

Page 42

... LBOTOT = 1 1.8 V DC) DD Min Max Unit 7 — 150 ps 2.6 — ns 1.9 — ns 1.1 — ns 1.1 — ns 1.2 — ns — 3.2 ns — 3.2 ns — 3.2 ns — 3.2 ns 0.9 — ns 0.9 — ns — 2.6 ns Freescale Semiconductor Notes 5 for is Notes 2 — — ...

Page 43

... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BV /2. DD Figure 23 provides the AC test load for the local bus. Output MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1 Symbol t LBKHOZ2 (first two letters of functional block)(signal)(state)(reference)(state) for outputs. For example, t LBK ...

Page 44

... Figure 24. Local Bus Signals (PLL Enabled) 1 Symbol t LBK t t LBKH/ LBK t LBKHKT t LBIVKH1 t LBIVKL2 t LBIXKH1 t LBIXKL2 t LBOTOT t LBKLOV1 t LBIXKH1 t LBIXKH2 = 3 with PLL DD Min Max Unit Notes 12 — 1.2 4.9 ns 7.4 — ns 6.75 — ns –0.2 — ns –0.2 — ns 1.5 — ns — 1.6 ns Freescale Semiconductor 2 — — — ...

Page 45

... LALE and any change in LAD. LBOTOT 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1 Symbol t LBKLOV2 ...

Page 46

... LGTA/LUPWAIT (which is captured on the rising edge of the internal clock). MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHKT t LBKLOV1 t LBKLOV2 t LBKLOV3 NOTE . In this mode, signals are launched at the rising LBKHKT t LBIVKH1 t LBIXKH1 t LBIVKL2 t LBIXKL2 t t LBKLOX1 t t LBKLOX2 t LBOTOT Freescale Semiconductor LBKLOZ1 LBKLOZ2 ...

Page 47

... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t t LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 ...

Page 48

... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKLOX1 LBKLOV1 t LBIVKH1 t LBKLOZ1 t LBIVKL2 t LBIXKL2 t LBIXKH1 Freescale Semiconductor ...

Page 49

... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t t LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 ...

Page 50

... Programmable Interrupt Controller In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods). MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKLOX1 LBKLOV1 t LBIVKH1 t LBKLOZ1 t LBIVKL2 t LBIXKL2 t LBIXKH1 Freescale Semiconductor ...

Page 51

... JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Input hold times: Valid times: Output hold times: MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol – ...

Page 52

... JTKHKL t JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD /2) Figure 32. TRST Timing Diagram 1 (continued) Min Max Unit the midpoint of the signal in question. TCLK Figure symbolizes JTAG device JTDVKH clock reference (K) JTG Ω JTGR t JTGF VM Freescale Semiconductor Notes 5 30). for ...

Page 53

... Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8533E PowerQUICC III Integrated Communications Host Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OV MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor VM t JTDVKH t ...

Page 54

... V DD — symbolizes I C timing (I2) I2DVKH clock reference (K) going to the high I2C symbolizes I I2PVKH min of the SCL signal) to bridge the SCL signal. I2CL Freescale Semiconductor Notes — — — — — — — — — — for 2 C clock ...

Page 55

... Low-level input voltage Input current ( DD) High-level output voltage ( Low-level output voltage (OV = min Note: 1. Note that the symbol this case, represents the OV IN MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ω Figure 34 Test Load 2 C bus I2DVKH I2KHKL t I2SXKL ...

Page 56

... Figure 36. GPIO AC Test Load Symbol –2mA mA symbol referenced in IN Symbol Typ Unit PIWID ns to ensure proper operation. PIWID Ω Min Max Unit 0 –0.3 0.8 V μA — ±5 2.4 — V — 0.4 V Table 1 and Table 2. Freescale Semiconductor Notes 1 Notes — — 2 — — ...

Page 57

... PCI 2.2 Local Bus PCRHFV Specifications. 9. The reset assertion timing requirement for HRESET is 100 μs. Figure 37 provides the AC test load for PCI. Output MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor provides the PCI AC timing specifications at 66 MHz. 1 Symbol t PCKHOV t PCKHOX ...

Page 58

... The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev PCIVKH CLK t PCKHOV t PCKHOZ Output t PCIXKH Freescale Semiconductor ...

Page 59

... Sometimes, it may be even different between the receiver input and driver output circuits within the same component also referred as the DC offset in some occasions. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor (or Differential Output Swing): OD – V SDn_TX SDn_TX ...

Page 60

... MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Differential Swing Differential Peak Voltage, V Differential Peak-Peak Voltage, V DIFFpp is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V DIFFp are specified in DD_SRDS2 – – B| DIFFp = 2*V (not shown) DIFFp Table 1 and Table 2. Freescale Semiconductor ) DIFFp-p ...

Page 61

... In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) 50 Ω Input Amp 50 Ω ...

Page 62

... Figure 43. Differential Reference Clock Input DC Requirements (External AC-Coupled) MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Section 16.2.1, “SerDes Reference Figure 43 shows the SerDes reference clock Figure 44 Vmax < 800 mV 100 mV < Vcm < 400 mV Vmin > Vmax < Vcm + 400 mV Vmin > Vcm - 400 mV Freescale Semiconductor shows Vcm ...

Page 63

... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

Page 64

... MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev SDn_REF_CLK 100 Ω differential PWB trace SDn_REF_CLK Clock driver vendor dependent source termination resistor SDn_REF_CLK 100 Ω differential PWB trace SDn_REF_CLK MPC8533EMP 50 Ω SerDes Refer. CLK Receiver 50 Ω MPC8533E 50 Ω SerDes Refer. CLK Receiver 50 Ω Figure 47 Freescale Semiconductor ...

Page 65

... It assumes the DC levels of the clock driver are compatible with MPC8533E SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip 33 Ω Clock Driver CLK_Out Figure 48. Single-Ended Connection (Reference Only) MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor SDn_REF_CLK 10nF 10nF R2 100 Ω differential PWB trace 10nF R2 SDn_REF_CLK Total 50 Ω ...

Page 66

... Figure 49. Differential Measurement Points for Rise and Fall Time MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min Rise Edge Rate Fall Edge Rate V +200 Rise-Fall Matching Figure 49. Figure 50. Fall Edge Rate Max Unit Notes 1.0 4.0 V/ 1.0 4.0 V/ — — –200 mV 2 — Freescale Semiconductor ...

Page 67

... Section 17, “PCI Express” Please note that external AC Coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in specification of each protocol section. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor SDn_REF_CLK V + 100 mV CROSS MEDIAN ...

Page 68

... PCI Express Base Specification. Rev. 1.0a. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Min Typ Max Units — 10 — ns — — 100 ps –50 — Freescale Semiconductor Notes 1 — — ...

Page 69

... Absolute delta of DC TX-CM-DC-LINE-DELTA common mode between D+ and D– V Electrical idle TX-IDLE-DIFFp differential peak output voltage MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Min Nom Max Unit 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations ...

Page 70

... Required well as D– DC Impedance during all states. — — 500 + ps Static skew between any two transmitter 2 UI lanes within a single link. 75 — 200 nF All transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. Comments Freescale Semiconductor ...

Page 71

... It is recommended that the recovered calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Min Nom Max Unit 0 — ...

Page 72

... See Note × |V – V RX-DIFFp-p RX-D+ RX-D– See Note 2. UI The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as T RX-MAX-JITTER = 1 – 0.6 UI. RX-EYE See Notes 2 and 3. Freescale Semiconductor | ...

Page 73

... Electrical idle detect RX-IDLE-DET-DIFFp-p threshold T Unexpected RX-IDLE-DET-DIFF- electrical idle enter ENTERTIME detect threshold integration time MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Min Nom Max Units — — 0.3 UI Jitter is defined as the measurement variation of the crossing points ( relation to a recovered TX UI. A recovered calculated over 3500 consecutive unit intervals of sample data ...

Page 74

... Skew across all lanes on a link. This includes variation in the length of SKP ordered set (for example, COM and one to five symbols) at the RX as well as any delay differences arising from the interconnect itself. Figure 54 should be used Figure 53). If the Figure Freescale Semiconductor 53) ...

Page 75

... D+ and D– not being exactly matched in length at the package pin boundary. D+ Package D+ Package D– Package Figure 54. Compliance Test/Measurement Load MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor NOTE Figure 53). Note that the series capacitors, CTX, are V > 175 mV RX-DIFFp-p-MIN ...

Page 76

... The package parameters for flip chip plastic ball grid array (FC-PBGA) are provided in Package outline Interconnects Ball pitch Ball diameter (typical) Solder ball (Pb-free) Note: 1. (FC-PBGA) without a lid. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 56. Package Parameters 1 Parameter PBGA 29 mm × 783 1 mm 0.6 mm 96.5% Sn 3.5% Ag Table 56. Freescale Semiconductor ...

Page 77

... Capacitors may not be present on all parts. Care must be taken not to short exposed metal capacitor pads. 7. All dimensions are symmetric across the package center lines, unless dimensioned otherwise. Figure 55. Mechanical Dimensions and Bottom Surface Nomenclature MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor of the MPC8533E FC-PBGA without a Lid Package Description 77 ...

Page 78

... MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE NOTE Table 57 Table 57. MPC8533E Pinout Listing Package Pin Number PCI for more details. Power Pin Type Notes Supply Freescale Semiconductor — — — 2 — — — — — ...

Page 79

... L19 LA[28:31] K16, K17, H17,G17 LCS[0:4] K18, G19, H19, H20, G16 LCS5/DMA_DREQ2 H16 MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number DDR SDRAM Memory Interface Local Bus Controller Interface Package Description Power Pin Type Notes Supply ...

Page 80

... IRQ[10]/DMA_DACK3 AE27 IRQ[11]/DMA_DDONE3 AE24 IRQ_OUT AD14 MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number DMA Programmable Interrupt Controller Power Pin Type Notes Supply I — — — — — — — — — — I I Freescale Semiconductor ...

Page 81

... TSEC3_RX_DV P8 TSEC3_RX_ER R11 TSEC3_TX_CLK L10 TSEC3_TX_EN N6 TSEC3_TX_ER L8 UART_CTS[0:1] AH8, AF6 UART_RTS[0:1] AG8, AG9 MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number Ethernet Management Interface Gigabit Reference Clock DUART Package Description Power Pin Type Notes Supply I/O OV — ...

Page 82

... MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number interface SerDes 1 SerDes 2 Power Pin Type Notes Supply I OV — — — — — — — — DD — — — — — — — — — DD Freescale Semiconductor ...

Page 83

... SYSCLK AH16 TCK AG28 TDI AH28 TDO AF28 TMS AH27 TRST AH22 MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number General-Purpose Output General-Purpose Input System Control Debug Clock JTAG Package Description Power Pin Type Notes Supply ...

Page 84

... Power for PCI OV DD and other standards (3.3 V) Power for LV DD TSEC1 interfaces (2.5 V, 3.3 V) Power for TV DD TSEC3 interfaces (2 and DDR2 DRAM I/O voltage (1.8 V, 2.5 V) Power for BV DD 2.5 V, 3.3 V) Freescale Semiconductor Notes — — — — — — ...

Page 85

... AE3, AE1, AE25, AF3, AH2 AGND_SRDS2 AF1 AVDD_LBIU C28 AVDD_PCI1 AH20 AVDD_CORE AH14 AVDD_PLAT AH18 MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number Power for e500 Package Description Power Pin Type Supply Power for core V DD (1.0 V) Core power for ...

Page 86

... Power for — SRDSPLL (1 — — Reference MVREF voltage signal for DDR — 200Ω to GND — 100Ω to GND — AVDD_SRDS ANALOG 200 Ω to GND I 100 Ω to GND I O AVDD_SRDS2 ANALOG — — . Freescale Semiconductor — — — 17 — — 17 — ...

Page 87

... GND. 28.For systems that boot from a local bus (GPCM)-controlled flash, a pull-up on LGPL4 is required. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Package Pin Number Section 19.3, “e500 Core PLL Ratio.” /GND planes internally and may be used by the core power supply to improve tracking DD ...

Page 88

... MHz Min 166 and Section 19.3, “e500 Core PLL Ratio,” Table 59 provides the clocking 1067 MHz Unit Notes Min Max 667 1067 MHz 1, 2 for ratio settings. Frequency Unit Notes Max 266 MHz 1, 2 for ratio Table 60): Freescale Semiconductor ...

Page 89

... The use of PCI_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of PCI_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 60. CCB Clock Ratio Binary Value of LA[28:31] Signals ...

Page 90

... Table 62. SEC Frequency Ratio Value (Binary SYSCLK (MHz) 41.66 66.66 83 Platform /CCB Frequency (MHz) — 333 333 415 400 500 333 533 375 417 500 CCB CLK:SEC CLK 1 2:1 2 3:1 100 111 133.33 — — 333 400 400 445 533 500 Freescale Semiconductor ...

Page 91

... Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1°C/W. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor for additional information. Maximum FIFO Speed for Reference Clocks TSECn_TX_CLK, TSECn_RX_CLK Table 65 ...

Page 92

... Table 67. MPC8533EThermal Model Value Die (7.6 × 8.4 × 0.75mm) Temperature dependent 6.5 Substrate (29 × 29 × 1.18 mm 1.0 Thermal Resistance (°C/W) 6.1 3.0 8.1 4.3 11.6 6.7 8.3 4.3 Figure 56. The for actual dimensions. Units — W/m•K W/m•K Freescale Semiconductor ...

Page 93

... Grid density lower than currently in the package library file will suffice for these simulations. The user will need to determine the optimal grid for their specific case. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Value Solder and Air (29 × 29 × 0.58 mm) 0.034 ...

Page 94

... Alpha Novatech408-567-8082 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Section 20.3.4, “Temperature Diode,” FC-PBGA Package Heat Sink Heat Sink Clip Adhesive or Die for more Figure 57. The heat sink should be Freescale Semiconductor ...

Page 95

... Internal Package Conduction Resistance For the packaging technology, shown in are as follows: • The die junction-to-case thermal resistance • The die junction-to-board thermal resistance MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 65, the intrinsic internal conduction thermal resistance paths Thermal 95 ...

Page 96

... The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Leads Radiation Convection Freescale Semiconductor ...

Page 97

... Internet: www.dow.com Shin-Etsu MicroSi, Inc.888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company800-347-4572 th 18930 West 78 St. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease ...

Page 98

... J = 0.1, and a power consumption ( 30°C + 5°C + (0.1°C/W + 1.0°C/W + θ versus airflow velocity for a Thermalloy heat sink SA of about 5°C/W, thus SA+ ) may be in the range of 5° may be about 1°C/W. Assuming a T INT ) of 5, the following D ) × Freescale Semiconductor ) I I ...

Page 99

... The ideality factor is defined as the deviation from the ideal diode equation nKT – Another useful equation is – MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Thermalloy #2328B Pin-fin Heat Sink (25 × 28 × 15 mm) 0.5 1 1.5 2 Figure 60. Approach Air Velocity (m/ 2.5 3 3.5 Thermal 99 ...

Page 100

... There are two PLLs for the SerDes block. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 100 is flowing H is flowing L –19 C) –23 Joules/K) × nT –4 –4 Section 19.2, “CCB/SYSCLK PLL Ratio.” Section 19.3, “e500 Core PLL Ratio.” Freescale Semiconductor ...

Page 101

... All traces should be kept short, wide, and direct Note 0805 sized capacitor is recommended for system initial bring-up. Figure 62. SerDes PLL Power Supply Filter Circuit MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor _PCI, AV _LBIU, and and preferably these voltages will be derived directly from Ω ...

Page 102

... SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 102 . and LV planes, to enable quick recharging of the power plane and and ensure low DD DD Freescale Semiconductor pin ...

Page 103

... OV components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals OV P MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor , ...

Page 104

... MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 104 and R are designed to be close to each other in value. Then Pad Data R P OGND Figure 63. Driver Impedance Measurement Table 68. Impedance Characteristics PCI 25 Target 25 Target Table 1. DD SW2 SW1 DDR DRAM Symbol 20 Target Target Z 0 Freescale Semiconductor , DD Unit W W ...

Page 105

... IC). Regardless of the numbering, the signal placement recommended in all known emulators. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Figure 65 allows the COP port to Figure ...

Page 106

... COP connector physical pinout. COP_RUN/STOP COP_SRESET COP_HRESET COP_CHKSTP_OUT MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 106 COP_TDO NC COP_TDI 3 4 COP_TRST 5 6 COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS KEY 13 No pin GND 15 16 Figure 64. COP Connector Physical Pinout Freescale Semiconductor ...

Page 107

... This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting SRESET causes a machine check interrupt to the e500 core. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor COP_HRESET COP_SRESET B A ...

Page 108

... All AD pins will be driven to the stable states after POR. Therefore, all ADs pins can be floating. • All PCI control pins can be grouped together and tied to OV • optional to disable PCI block through DEVDISR register after POR reset. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 108 through a single 10-kΩ resistor. DD Freescale Semiconductor ...

Page 109

... Refer to Table 2 for operating temperature ranges. Temperature is independent of tier and varies per product. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Power-On Hours Part-time/ Full-Time PC's, consumer electronics, office automation, SOHO networking, portable telecom products, PDAs, etc. Typically Full-Time Installed telecom equipment, work stations, servers, warehouse equipment, etc ...

Page 110

... Figure 66. MPCnnnnCHXAAXB MMMMM CCCCC ATWLYYWW FC-PBGA AA X Processor Platform Revision 2 Frequency Frequency AL = 667 MHz F = 333 MHz Blank = Rev 800 MHz G = 400 MHz 1.1 1.1 1000 MHz J = 533 MHz A = Rev. 2 1067 MHz Freescale Semiconductor B Level ...

Page 111

... Update in Improvement to Update Figure 55 Update in 0 04/2008 Initial release. MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Substantive Change(s) Table 70. Section 1.1, “Key Features,” Table 57. Table 56. Section 20.3.4, “Temperature Diode,” Table 56 Package Parameters from 95.5%sn to 96.5%sn 35, removed note 1 and renumbered remaining note. Section 21.3, “ ...

Page 112

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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