MPC8347EVVALFB Freescale Semiconductor, MPC8347EVVALFB Datasheet
MPC8347EVVALFB
Specifications of MPC8347EVVALFB
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MPC8347EVVALFB Summary of contents
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... Host Processor Hardware Specifications. See Section 23.1, “Part Numbers Fully Addressed by This Document,” for silicon revision level determination. © Freescale Semiconductor, Inc., 2005–2009. All rights reserved. Document Number: MPC8347EEC Rev. 11, 02/2009 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 4 ...
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... MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev e300 Core 2 C Interrupt 32KB 32KB Controller D-Cache I-Cache 10/100/1000 10/100/1000 Ethernet Ethernet Figure 1. MPC8347E Block Diagram Figure 1 shows the major DDR SDRAM Local Bus Controller SEQ PCI DMA Freescale Semiconductor ...
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... IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs): — Public key execution unit (PKEU) : – RSA and Diffie-Hellman algorithms MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Overview 3 ...
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... External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI) • Universal serial bus (USB) multi-port host controller — Can operate as a stand-alone USB host controller – USB root hub with one or two downstream-facing ports MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... Concurrent execution across multiple channels with programmable bandwidth control — All channels accessible to local core and remote PCI masters — Misaligned transfer capability MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 2 C interfaces 2 C-1 EPROM by boot sequencer embedded ...
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... Real-time clock — Software watchdog timer — Eight general-purpose timers • Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan • Integrated PCI bus and SDRAM clock generation MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... IN REF the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 3. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol ...
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... DD GND Not to Exceed 10 interface Recommended Unit Value 1.2 V ± 1.2 V ± 2.5 V ± 125 mV V 3.3 V ± 330 mV V 2.5 V ± 125 mV 3.3 V ± 330 mV V 2.5 V ± 125 mV 3.3 V ± 330 /OV / Freescale Semiconductor Notes 1 1 ...
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... To minimize the time that I/O pins are actively driven recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 11 ns (Min) +7 ...
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... Table 5. = 105°C, and a Dhrystone benchmark J target, and I 105°C, and an J Freescale Semiconductor Unit ...
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... MHz, 32 bits 66 MHz, 32 bits 50 MHz, 32 bits TSEC I/O MII load = 25 pF GMII or TBI RGMII or RTBI USB 12 MHz 480 MHz Other I/O 1 TBGA package only. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor DDR2 DDR1 (3.3 V) (3.3 V) (1.8 V) (2.5 V) — ...
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... KHK CLKIN — — Min Max 2 0 –0.3 0 — ± — ± — ±50 IN Table 7 provides the clock input Typical Max Unit — 66 MHz — — ns 1.0 2.3 ns — — ±150 ps Freescale Semiconductor Unit V V μA μA μA Notes 1, 6 — ...
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... PORESET when the MPC8347E is in PCI host mode Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347E is in PCI agent mode MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Symbol Condition Min V 2 – ...
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... MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Min 0 — 1 Table 10. PLL and DLL Lock Times Min — 7680 Section 19, “Clocking.” Max Unit Notes — — PCI_SYNC_IN Max Unit Notes μs 100 122,880 csb_clk cycles 1, 2 Freescale Semiconductor ...
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... DDR capacitance. Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Note: 1. This parameter is sampled MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor NOTE Section 23.1, “Part Numbers Fully Addressed by This Symbol Min GV 2.375 DD 0.49 × GV ...
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... MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev 2.5 V ± 5%. DD Symbol Min V — 0.31 IH REF t — DISKEW 333 MHz 266 MHz t MCK D0 t DISKEW DDR Input Timing Diagram Figure 4. Max Unit MV – 0.31 V REF 750 1125 timing parameter. DISKEW D1 t DISKEW Freescale Semiconductor Notes 1 ...
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... MCS(n) output hold with respect to MCK MCK to MDQS MDQ/MECC/MDM output setup with respect to MDQS MDQ/MECC/MDM output hold with respect to MDQS MDQS preamble start MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor of 2.5 V ± 5 Symbol Min t 6 MCK ...
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... AOSKEW MCK[n] MCK[n] t MCK t AOSKEWmax) CMD t AOSKEW(min) CMD NOOP Measurement AOSKEW Max Unit 0.3 ns memory clock reference MCK describes the DDR timing (DD) DDKHMH can be modified through control DDKHMH follows the symbol DDKHMP NOOP Freescale Semiconductor Notes 7 for ...
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... DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the system topology heavily loaded system is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor = 50 Ω Ω ...
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... DDR SDRAM Table 16. Expected Delays for Address/Command 4 devices (12 pF) 9 devices (27 pF) 36 devices (108 pF compensation capacitor 36 devices (108 pF compensation capacitor MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Load Delay Unit 3.0 ns 3.6 ns 5.0 ns 5.2 ns Freescale Semiconductor ...
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... Oversample rate Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8 th sampled each 16 sample. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Symbol Table 18. DUART AC Timing Specifications ...
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... IH V — GND IL IN symbol referenced in Table 1 IN Section 8.3, Table 20 are based on a 2.5-V CMOS Min Max 2.97 3.63 = Min 2. 0 Min GND 0.50 — 2 0.3 DD — –0.3 0.90 — 40 –600 — and Table 2. supply. DD Freescale Semiconductor Unit μA μA ...
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... GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate GTX letter: R (rise (fall). 2. This symbol represents the external GTX_CLK125 signal and does not follow the original symbol naming convention. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Symbol Conditions LV — ...
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... In general, the clock GRX t GTXR Min Typ Max — 8.0 — 40 — 60 2.0 — — 0.5 — — — — 1.0 — — 1.0 for inputs symbolizes GMII receive timing GRDVKH clock reference (K) going RX Freescale Semiconductor Unit GRX ...
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... For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t GRX t ...
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... Figure 11. TSEC AC Test Load t MTXR Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII receive timing MRDVKH clock reference (K) going to MRX Ω Freescale Semiconductor Unit for inputs MRX ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t MRX ...
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... TRX t TTXR t TTKHDX Min Typ Max 16.0 7.5 — 8.5 40 — 60 2.5 — — 1.5 — — 0.7 — 2.4 0.7 — 2.4 symbolizes TBI receive timing TRDVKH clock reference (K) going to TRX represents the TBI TRX Freescale Semiconductor Unit for inputs ...
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... Duty cycle reference This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t TRX t t TRXH ...
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... PHY) Figure 15. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR t RGT t SKRGT t SKRGT Freescale Semiconductor ...
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... Input low voltage Input high current Input low current Note: 1. The symbol this case, represents the LV IN MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Section 8.1, “Three-Speed Ethernet Controller (TSEC)— Characteristics.” Table 28 and Symbol Conditions LV — ...
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... For example MDC t t MDCH MDCF t MDDVKH t MDDXKH t MDKHDX Typ Max Unit 2.5 — MHz 400 — ns — — ns — 170 ns — — ns — — ns — — for inputs symbolizes management data MDKHDX t MDCR Freescale Semiconductor Notes 2 3 ...
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... For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 31. USB DC Electrical Characteristics Symbol ...
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... AC test load and signals for the USB, respectively. Output USB0_CLK/USB1_CLK/DR_CLK Input Signals Output Signals: MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Ω Ω Figure 17. USB AC Test Load t USIVKH t t USKHOV USKHOX Figure 18. USB Signals USIXKH Freescale Semiconductor ...
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... Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Output hold from local bus clock (except LAD/LDP and LALE) MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Symbol Min V 2 ...
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... LSYNC_IN to 0.4 × Symbol t LBK t LBIVKH t LBIXKH t LBOTOT1 t LBOTOT2 t LBOTOT3 Min Max Unit Notes 1 — — 3 for inputs symbolizes local bus timing (LB) LBIXKH1 of the signal in question for 3 Min Max Unit Notes 15 — — 1.0 — 1.5 — — 2.5 — Freescale Semiconductor ...
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... DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 19 provides the AC test load for the local bus. Output MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 1 Symbol t LBKLOV t ...
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... Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev LBIVKH t LBKHOV t LBKHOZ t t LBKHOV LBKHOX t LBKHOZ t t LBKHOV LBKHOX t LBOTOT t LBKHLR t LBIXKH t LBKLOV t t LBKHOZ LBKLOV t t LBKLOV LBOTOT t LBIXKH t LBIXKH t LBIXKH t LBIVKH t LBIVKH Freescale Semiconductor ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t ...
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... Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ t LBKLOV t LBIVKH t t LBKHOZ t LBKLOV t LBIXKH t LBIXKH LBIVKH Freescale Semiconductor ...
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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t LBKHOZ1 t LBKHOV1 t LBIVKH2 t ...
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... JTIVKH t JTDXKH t TMS, TDI JTIXKH t JTKLDV t TDO JTKLOV Min Max OV – –0.3 0.8 ±5 2.4 — — 0.5 — 0.4 Figure 27 through 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 4 — — 10 — Freescale Semiconductor Unit V V μ ...
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... Figure 26. AC Test Load for the JTAG Interface Figure 27 provides the JTAG clock input timing diagram. JTAG External Clock Figure 27. JTAG Clock Input Timing Diagram MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 2). 2 Symbol t JTKLDX ...
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... VM = Midpoint Voltage (OV DD /2) Figure 28. TRST Timing Diagram VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 29. Boundary-Scan Timing Diagram VM t JTIVKH t JTKLOV t JTKLOZ VM = Midpoint Voltage ( JTDXKH Input Data Valid Output Data Valid VM t JTIXKH Input Data Valid Output Data Valid Freescale Semiconductor ...
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... Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 2 C interface of the MPC8347E. 2 Table 38 Electrical Characteristics of 3.3 V ± ...
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... OV V — symbolizes I C timing (I2) with I2DVKH clock reference (K) going to the high (H) I2C symbolizes I I2PVKH (min) of the SCL signal) to bridge the SCL signal. I2CL AC parameter. I2CF Ω I2KHKL I2CF t I2CR t I2PVKH P Freescale Semiconductor Unit ns μs μ for inputs 2 C clock I2C S ...
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... Table 41. PCI AC Timing Specifications at 66 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 40. PCI DC Electrical Characteristics Symbol Test Condition ≥ ...
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... PCI timing (PC) with respect to the time hard reset (R) went PCRHFV = 50 Ω Ω Figure 33. PCI AC Test Load 1 (continued) Max Unit Notes — for inputs symbolizes PCI timing (PC) with PCIVKH , reference (K) going SYS Max Unit Notes — — — for inputs symbolizes PCI timing (PC) with PCIVKH , reference (K) going SYS Freescale Semiconductor ...
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... PCI input AC timing diagram. CLK Input Figure 35 shows the PCI output AC timing diagram. CLK Output Delay High-Impedance Output MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t PCIVKH Figure 34. PCI Input AC Timing Diagram t PCKHOV Figure 35. PCI Output AC Timing Diagram t PCIXKH t ...
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... Timer inputs are required to be valid for at least t MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Symbol Condition – ensure proper operation. TIWID Min Max Unit 2 0 –0.3 0.8 V μA ±5 2.4 — V — 0.5 V — 0 Symbol Min Unit TIWID Freescale Semiconductor ...
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... Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external synchronous logic. GPIO inputs must be valid for at least t MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Symbol Condition V ...
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... MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Symbol Condition Min V 2 –0 8.0 mA — 3.2 mA — not relevant for those pins ensure proper operation in edge triggered mode. PICWID 1 Max Unit Notes 0.8 V μA ± Symbol Min Unit PICWID Freescale Semiconductor ...
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... SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 49. SPI DC Electrical Characteristics Symbol Condition ...
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... Note: The clock edge is selectable on SPI. Figure 38. SPI AC Timing in Master Mode (Internal Clock) Diagram MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Ω Figure 36. SPI AC Test Load Table 50. Note that although the specifications t NEIXKH t NEKHOX t NIIXKH t NIIVKH t NIKHOX Ω Freescale Semiconductor ...
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... Package outline Interconnects Pitch Module height (typical) Solder balls Ball diameter (typical) MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 35 mm × 672 1. Sn/36 Pb/2 Ag (ZU package) 95.5 Sn/0.5 Cu/4Ag (VV package) 0.64 mm Package and Pin Listings Section 18 ...
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... A, the seating plane, is determined by the spherical crowns of the solder balls. 5.Parallelism measurement must exclude any effect of mark on top surface of package. Figure 39. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8347E TBGA MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... Interconnects Pitch Module height (maximum) Module height (typical) Module height (minimum) Solder balls Ball diameter (typical) MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 29 mm × 620 1.00 mm 2.46 mm 2. Sn/36 Pb/2 Ag (ZQ package) 95.5 Sn/0.5 Cu/4Ag (VR package) ...
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... A. 4.Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 40. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8347E PBGA MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... PCI_GNT0 PCI_GNT1/CPCI1_HS_LED PCI_GNT2/CPCI1_HS_ENUM PCI_GNT[3:4] M66EN MDQ[0:63] MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 51. MPC8347E (TBGA) Pinout Listing Package Pin Number PCI B34 C33 G30, G32, G34, H31, H32, H33, H34, J29, J32, J33, L30, K31, K33, K34, ...
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... AM19, AP20, AK19, AN20, AL20, AP21, AN21 AM21 AP22 AN22 AM22 AK21, AP23, AN23, AP24, AK22 AN24, AL23, AP25, AN25 AK23, AP26, AL24, AM25 Power Pin Type Notes Supply — — — — — — 8 — — Freescale Semiconductor ...
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... GPIO1[9]/GTM1_TIN4/GTM2_TIN3 GPIO1[10]/GTM1_TGATE4/GTM2_TGATE3 GPIO1[11]/GTM1_TOUT4/GTM2_TOUT3 MPH1_D0_ENABLEN/DR_D0_ENABLEN MPH1_D1_SER_TXD/DR_D1_SER_TXD MPH1_D2_VMO_SE0/DR_D2_VMO_SE0 MPH1_D3_SPEED/DR_D3_SPEED MPH1_D4_DP/DR_D4_DP MPH1_D5_DM/DR_D5_DM MPH1_D6_SER_RCV/DR_D6_SER_RCV MPH1_D7_DRVVBUS/DR_D7_DRVVBUS MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number AN26 AK24 AP27 AL25 AJ24 AN27 AP28 AL26 AM27 AN28, AK26, AP29 ...
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... C31 B32 A32 A33 C32 D31 E30 B33 Programmable Interrupt Controller AN33 C19 C22, A22, D21, C21, B21 A21 C20 Ethernet Management Interface A7 E9 Power Pin Type Notes Supply DD1 I DD1 Freescale Semiconductor ...
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... TSEC2_RX_ER/GPIO1[25] TSEC2_TXD[7]/GPIO1[31] TSEC2_TXD[6]/DR_XCVR_TERM_SEL TSEC2_TXD[5]/DR_UTMI_OPMODE1 TSEC2_TXD[4]/DR_UTMI_OPMODE0 TSEC2_TXD[3:0]/GPIO1[17:20] TSEC2_TX_ER/GPIO1[24] TSEC2_TX_EN/GPIO1[12] TSEC2_TX_CLK/GPIO1[30] MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number Gigabit Reference Clock C8 A17 F12 D10 A11 B11 B17 B16, D16, E16, F16 ...
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... AP32 AN31 AM31 SPI AN32 AP33 AK30 AL31 Clocks AN9, AP9, AM10, AN10, AJ11 AK12 AP11 AM32 AM9 JTAG E20 F20 B20 A20 B19 Test D22 AL13 PMC A18 Power Pin Type Notes Supply Freescale Semiconductor ...
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... GND MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number System Control C18 B18 D18 Thermal Management K32 Power and Ground Signals L31 AP12 AE1 AJ13 A1, A34, C1, C7, C10, C11, C15, C23, C25, C28, D1, D8, D20, D30, E7, E13, ...
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... AL29, AL30, AM20, AM23, AM24, AM26, AM28, AN11, AN13 M3 AD2 Power Pin Type Notes Supply Power for three-speed Ethernet #2 I/O (2.5 V, 3.3 V) Power for core V DD (1.2 V) PCI, 10/100 OV DD Ethernet, and other standard (3 DDR reference voltage I DDR reference voltage Freescale Semiconductor ...
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... PCI1_AD[31:0] PCI1_C/BE[3:0] PCI1_PAR PCI1_FRAME PCI1_TRDY MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number No Connection W32, AA31, AA32, AA33, AA34, AB31, AB32, AB33, AB34, AC29, AC31, AC33, AC34, AD30, AD32, AD33, AD34, AE29, AE30, AH32, ...
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... AE27, AE26, AE20, AH18, AG10, AF5, AC3, AA1, AH13 AF10, AF11 AF13, AF15, AG16, AD16, AF17, AH20, AH19, AH21, AD18, AG21, AD13, AF21, AF22, AE1, AA5 AD10 AF7 Power Pin Type Notes Supply Freescale Semiconductor ...
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... LGPL4/LGTA/LUPWAIT/LPBSE LGPL5/cfg_clkin_div LCKE LCLK[0:2] LSYNC_OUT LSYNC_IN MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number AG6 AE7, AH7, AH4, AF2 AG23, AH23 AH15, AE24, AE2, AF14, AE23, AD3 AG15, AD23, AE3, AG14, AF24, AD2 Pins Reserved for Future DDR2 ...
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... K24 G26 USB Port 1 C28 F25 B28 C27 D26 E25 C26 D25 B26 E24 A27 C25 A26 B25 A25 USB Port 0 D24 C24 Power Pin Type Notes Supply Freescale Semiconductor ...
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... EC_GTX_CLK125 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER/GPIO2[26] TSEC1_RXD[7:4]/GPIO2[22:25] TSEC1_RXD[3:0] TSEC1_TX_CLK MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number B24 A24 D23 C23 B23 A23 D22 C22 B22 A22 ...
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... AB26, AB27, AA24, AB28 R27 AD28 R26 DUART D5 D6 interface SPI D7 Power Pin Type Notes Supply I DD1 O LV DD1 I I I/O LV DD2 O LV DD2 I LV DD2 I/O LV DD2 I I/O LV DD2 I I I/O LV DD2 I I DD2 Freescale Semiconductor ...
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... PCI_SYNC_OUT RTC/PIT_CLOCK CLKIN TCK TDI TDO TMS TRST TEST TEST_SEL QUIESCE PORESET HRESET SRESET THERM0 MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number Clocks Y1, W3 JTAG H27 H28 M24 J27 K26 Test F28 T3 PMC ...
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... Power for DDR GV DD DRAM I/O voltage (2.5 V) Power for three-speed Ethernet #1 and for Ethernet management interface I/O (2.5 V, 3.3 V) Power for three-speed Ethernet #2 I/O (2.5 V, 3.3 V) Power for core V DD (1.2 V) PCI, 10/100 OV DD Ethernet, and other standard (3.3 V) Freescale Semiconductor ...
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... For proper functionality of the device, this pin must be pulled up or actively driven high during a hard reset. No external pull-down resistors are allowed to be attached to this net. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number AF19 ...
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... Div /2 Clock lbiu_clk Unit /n To Local Bus Memory LBIU Controller DLL csb_clk to Rest of the Device PCI Clock Divider Figure 41. MPC8347E Clock Subsystem 6 DDR MCK[0:5] Memory 6 Device MCK[0:5] LCLK[0:2] Local Bus LSYNC_OUT Memory Device LSYNC_IN PCI_CLK/ PCI_SYNC_IN PCI_SYNC_OUT 5 PCI_CLK_OUT[0:4] Freescale Semiconductor ...
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... TSEC2 Security core USB DR, USB MPH PCI and DMA complex MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 53 specifies which units have a configurable clock frequency. Table 53. Configurable Clock Units Default Frequency csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 ...
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... MHz 400 MHz 200–333 200–400 100–266 16.67–133 25–66 133 133 Freescale Semiconductor Unit MHz MHz MHz MHz MHz MHz MHz Unit MHz MHz MHz MHz MHz MHz ...
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... PCI_CLK) and the internal coherent system bus clock (csb_clk). and Table 58 show the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 56. System PLL Multiplication Factors System PLL Multiplication RCWL[SPMF] Factor 0000 × ...
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... Input Clock Frequency (MHz) 25 33.33 66.67 csb_clk Frequency (MHz) 133 100 200 100 133 266 125 166 333 150 200 175 233 200 266 225 300 250 333 275 300 325 133 100 200 133 266 166 333 200 233 Freescale Semiconductor ...
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... RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 59 not listed in Table 59 should be considered as reserved. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor csb_clk : SPMF Input Clock 16.67 2 Ratio ...
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... Table 59. e300 Core PLL Configuration core_clk : csb_clk Ratio PLL bypassed 1:1 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3:1 1 VCO Divider PLL bypassed (PLL off, csb_clk clocks core directly Freescale Semiconductor ...
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... The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF and COREPLL settings given in the table. 2 The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 60. Suggested PLL Configurations 533 MHz Device Input CSB ...
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... MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Symbol Value Unit °C θJA °C θJMA °C θJMA °C θJMA °C θJMA °C θJMA °C/W R 3.8 θJB °C/W R 1.7 θJC ψ °C Symbol Value Unit °C θJA °C θJMA °C θJMA °C θJMA °C θJB Freescale Semiconductor Notes Notes ...
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... The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor × where P ...
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... When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance θ JA MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev × θ Ψ determine the junction temperature and a measure of the JT Ψ × θ θ Freescale Semiconductor ...
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... Heat Sink Assuming Thermal Grease AAVID 30 × 30 × 9.4 mm pin fin AAVID 30 × 30 × 9.4 mm pin fin MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor . For instance, the user can change the size of the heat θ CA Air Flow ...
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... MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev × PBGA Air Flow Thermal Resistance 2 m/s 8.8 Natural convection 11.3 1 m/s 8.1 2 m/s 7.5 Natural convection 9.1 1 m/s 7.1 2 m/s 6.5 Natural convection 10.1 1 m/s 7.7 2 m/s 6.6 1 m/s 6.9 603-224-9988 408-567-8082 818-842-7277 408-436-8770 Freescale Semiconductor ...
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... When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 800-522-2800 603-635-5102 781-935-4850 ...
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... where junction temperature (° case temperature of the package (° junction-to-case thermal resistance (°C/W) θ power dissipation (W) D MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev × θ Freescale Semiconductor ...
Page 91
... Figure 42 shows the PLL power supply filter circuit MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Section 19.1, “System PLL Configuration.” Section 19.2, “Core PLL Configuration.” , and preferably these voltages are derived directly from V Figure 42, one to each of the four AV 10 Ω ...
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... MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev required. Unused active high inputs should C). is trimmed until the voltage at the pad equals and LV pin of the and GND pins (see Figure 43). The DD and R are designed to be close to each N Freescale Semiconductor , and , DD DD ...
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... However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor ...
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... C pins, the Ethernet Management MDIO pin, and IPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, refer to application note AN2931, PowerQUICC™ Design Checklist. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
Page 95
... In Section 23, “Ordering Information,” replaced first paragraph and added a note. In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced first paragraph. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 66. Document Revision History Substantive Change(s) Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list. ...
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... Table 36, “JTAG Interface DC Electrical Characteristics,” 1.8-V values for DDR2; added DD Document,” replaced third sentence of first from 0.5 to 1.0. TTKHDX from 70 to MDKHDX from 1.7 to 2.2. LBIVKH2 input high voltage min to 2.0. IH Freescale Semiconductor ...
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... Table 66. Document Revision History (continued) Revision Date 1 4/2005 Table 1: Addition of note 1 Table 48: Addition of Therm0 (K32) Table 49: Addition of Therm0 (B15) 0 4/2005 Initial release. MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Document Revision History Substantive Change(s) 97 ...
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... ZQ = PBGA Free PBGA for more information on available package types. Table 68. SVR Settings Package SVR (Rev. 1.0) TBGA TBGA aa a Processor Platform 3 Frequency Frequency e300 core D = 266 Blank = 1.1 4 speed F = 333 AD = 266 AG = 400 AJ = 533 AL = 667 8052_0010 8053_0010 Freescale Semiconductor r Revision Level or 1.0 ...
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... MPC8347E MPC8347 23.2 Part Marking Parts are marked as in the example shown in Figure 44. Freescale Part Marking for TBGA or PBGA Devices MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 68. SVR Settings (continued) PBGA PBGA . Figure 44 MPCnnnnetppaaar core/platform MHZ ...
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... Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 100 Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Ordering Information 101 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...