668-0011 Rabbit Semiconductor, 668-0011 Datasheet - Page 256

• Manufacturer Part Number: 668-0011
• Description: IC MPU RABIT3000A 55.5MHZ128LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0011

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 3000 8-Bit
• Speed: 55.5MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Features: -
• Other names: 316-1043

When the doubler is used, the duty cycle of the clock becomes a critical parameter. The
duty cycle should be measured at the separate clock output pin (pin 2). The minimum
period must be increased by any amount that the clock high time is greater or less than
specified in the duty-cycle requirement.
For example, consider a design where the spreader and doubler are enabled, with 8 ns
nominal delay in the doubler. The high and low clock are equal to within 1 ns. This violates the
duty cycle requirement by 3 ns since (clock low - clock high) can be as small as -1 ns, but
the requirement is that it not be less than 2 ns. Thus, 3 ns must be added to the minimum
period of 21 ns, giving a minimum period of 24 ns and a maximum frequency of 41.6 MHz
(commercial).
246
No doubler or
spreader
Spreader only
normal
Spreader only
strong
Doubler only
(8 ns delay)
Doubler only
(internal 50%
clock)
Spreader
normal with
doubler
(8 ns delay)
Spreader
normal with
doubler (8 ns
delay), internal
50% clock
Spreader only
strong
Spreader strong
with doubler
(8 ns delay)
Conditions
Table 27-11. Maximum Clock Speeds at 3.3 V [Preliminary]
Minimum
Commercial Ratings
Period
(ns)
21.5
17
20
21
19
20
21
24
23
Frequency
Maximum
(MHz)
58.8
50.0
47.6
52.6
47.6
41.6
46.5
43.5
50
Minimum
Period
Industrial Ratings
(ns)
22.5
18
21
22
20
21
22
25
24
Rabbit 3000 Microprocessor User’s Manual
Frequency
Maximum
(MHz)
55.5
47.6
45.4
50.0
47.6
45.4
40.0
45.0
41.6
1 > (clock low -
clock high) > 0
1 > (clock low -
clock high) > -1
4 > (clock low -
clock high) > 2
1 > (clock low -
clock high) > -1
8 > (clock low -
clock high) > 6
Requirements
Duty Cycle
(ns)