N80960SB16 Intel, N80960SB16 Datasheet

N80960SB16

Manufacturer Part Number

N80960SB16

Description

IC MPU I960SB 16MHZ 84-PLCC

Manufacturer

Intel

Datasheet

1.N80960SB16.pdf (38 pages)

Specifications of N80960SB16

Rohs Status

RoHS non-compliant

Processor Type

i960

Features

SB suffix, 32-Bit, 512 Byte Cache

Speed

16MHz

Voltage

Mounting Type

Surface Mount

Package / Case

84-PLCC

Other names

803883

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The 80960SB is a member of Intel’s i960

embedded applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in

interrupt controller. The 80960SB has a large register set, multiple parallel execution units and a 16-bit burst

bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess

of 5 million instructions per second

applications including non-impact printers, network adapters and I/O controllers.

* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent

licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

Corporation)

High-Performance Embedded Architecture

— 16 MIPS* Burst Execution at 16 MHz

— 5 MIPS Sustained Execution at 16 MHz

512-Byte On-Chip Instruction Cache

— Direct Mapped

— Parallel Load/Decode for Uncached

Multiple Register Sets

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored

— Register Scoreboarding

Pin Compatible with 80960SA

INSTRUCTION

FETCH UNIT

Instructions

On-Chip

REGISTERS

80-BIT FP

FOUR

80-BIT

FPU

EMBEDDED 32-BIT MICROPROCESSOR

INSTRUCTION

32-BIT GLOBAL

Figure 1. The 80960SB Processor’s Highly Parallel Architecture

REGISTERS

512-BYTE

SIXTEEN

CACHE

WITH 16-BIT BURST DATA BUS

. The 80960SB is well-suited for a wide range of cost sensitive embedded

INSTRUCTION

64- BY 32-BIT

DECODER

LOCAL

CACHE

32-bit processor family, which is designed especially for low cost

80960SB

November 1993

INSTRUCTION

SEQUENCER

INSTRUCTION

EXECUTION

MICRO-

32-BIT

UNIT

Built-in Interrupt Controller

— 4 Direct Interrupt Pins

— 31 Priority Levels, 256 Vectors

Built-In Floating Point Unit

— Fully IEEE 754 Compatible

Easy to Use, High Bandwidth 16-Bit Bus

— 25.6 Mbytes/s Burst

— Up to 16 Bytes Transferred per Burst

32-Bit Address Space, 4 Gigabytes

80-Lead Quad Flat Pack (EIAJ QFP)

— 84-Lead Plastic Leaded Chip Carrier

Software Compatible with

80960KA/KB/CA/CF Processors

(PLCC)

INSTRUCTION

MICRO-

ROM

CONTROL

32-BIT

LOGIC

BUS

Order Number: 272207-002

ADDRESS

32-BIT

16-BIT

BURST

BUS

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