A80960KB25 Intel, A80960KB25 Datasheet
A80960KB25
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A80960KB25 Summary of contents
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... INSTRUCTION INSTRUCTION INSTRUCTION FETCH UNIT CACHE Figure 1. The 80960KB Processor’s Highly Parallel Architecture © INTEL CORPORATION, 2004 80960KB Built-in Interrupt Controller — 31 Priority Levels, 256 Vectors — 3.4 µs Latency @ 25 MHz Easy to Use, High Bandwidth 32-Bit Bus — 66.7 Mbytes/s Burst — ...
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... Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice ...
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EMBEDDED 32-BIT MICROPROCESSOR 1.0 THE i960® PROCESSOR .......................................................................................................................... 1 1.1 Key Performance Features ................................................................................................................. 2 1.1.1 Memory Space And Addressing Modes ................................................................................... 4 1.1.2 Data Types ............................................................................................................................... 4 1.1.3 Large Register Set ................................................................................................................... 4 1.1.4 Multiple Register Sets .............................................................................................................. 5 ...
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Contents FIGURES Figure 1. 80960KA Programming Environment ........................................................................................ 1 Figure 2. Instruction Formats .................................................................................................................... 4 Figure 3. Multiple Register Sets Are Stored On-Chip ............................................................................... 6 Figure 4. Connection Recommendations for Low Current Drive Network .............................................. 11 Figure 5. Connection Recommendations ...
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TABLES Table 1. 80960KA Instruction Set ............................................................................................................ 3 Table 2. Memory Addressing Modes ....................................................................................................... 4 Table 3. 80960KA Pin Description: L-Bus Signals ................................................................................... 8 Table 4. 80960KA Pin Description: Support Signals ............................................................................... 9 Table 5. DC Characteristics ................................................................................................................... 15 Table ...
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... THE i960 PROCESSOR The 80960KB is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in interrupt controller. The 80960KB has a large register set, multiple parallel execution units and a high-bandwidth burst bus ...
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... Key Performance Features The 80960 architecture is based on the most recent advances in microprocessor technology and is grounded in Intel’s long experience in the design and manufacture of embedded microprocessors. Many features contribute to the 80960KB’s exceptional performance: 1. Large Register Set. Having a large number of registers reduces the number of times that a processor needs to access memory ...
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Data Movement Arithmetic Load Add Store Subtract Move Multiply Load Address Divide Remainder Modulo Shift Comparison Compare Unconditional Branch Conditional Compare Conditional Branch Compare and Increment Compare and Branch Compare and Decrement Debug Miscellaneous Modify Trace Controls Atomic Add Mark ...
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Control Compare and Branch Register to Register Memory Access—Short Memory Access—Long 1.1.1 Memory Space And Addressing Modes The 80960KB offers a linear environment so that all programs running on the processor are contained in a single address space. Maximum ...
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The term global refers to the fact that these registers retain their contents across procedure calls. The local registers, on the other hand, are procedure specific. For ...
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REGISTER CACHE ONE OF FOUR LOCAL REGISTER SETS Figure 4. Multiple Register Sets Are Stored On-Chip 1.1.7 Floating-Point Arithmetic In the 80960KB, floating-point arithmetic has been made an integral part of the architecture. Having the floating-point unit integrated on-chip ...
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... CHMOS The 80960KB is fabricated using Intel’s CHMOS IV (Complementary High Speed Metal Oxide Semicon- ductor) process. The 80960KB is currently available in 16, 20 and 25 MHz versions. ...
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Table 4. 80960KB Pin Description: L-Bus Signals (Sheet NAME TYPE CLK2 I SYSTEM CLOCK provides the fundamental timing for 80960KB systems divided by two inside the 80960KB and four 80-bit registers (FP0 through FP3) ...
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Table 4. 80960KB Pin Description: L-Bus Signals (Sheet NAME TYPE BE3:0 O BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are used in the current bus cycle. BE3 corresponds to LAD31:24; ...
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Table 5. 80960KB Pin Description: Support Signals (Sheet NAME TYPE FAILURE O INITIALIZATION FAILURE indicates that the processor did not initialize correctly. After RESET deasserts and before the first bus transaction begins, FAILURE O.D. asserts while ...
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Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance is reduced by shortening board traces between the processor and decoupling capacitors as much as possible. 2.3 Connection Recommendations For reliable operation, always connect unused inputs ...
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MHz 20 MHz 16 MHz Figure 7. Typical Supply Current vs. Case Temperature TEMP = +22°C @5.5V @5.0V @4.5V Figure 8. Typical Current vs. Frequency (Room Temp) 12 380 360 340 320 300 ...
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TEMP = +22°C @5.5V @5.0V @4.5V Figure 9. Typical Current vs. Frequency (Hot Temp) (TEMP = +85° 4.5V) CC 0.8 0.6 0.4 0.2 0 OUTPUT LOW CURRENT(mA) Figure 10. Worst-Case Voltage vs. Output Current ...
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Since the open-drain outputs sink current, only the I legs of the bridge OL are necessary and the I legs are not used. When OH the 80960KB driver under test is turned off, the ...
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Absolute Maximum Ratings Operating Temperature(PGA)................... 0°C to +85°C Case (PQFP) ............. 0°C to +100°C Case Storage Temperature .................................... –65°C to +150°C Voltage on Any Pin .................................. –0.5V to VCC +0.5V Power Dissipation ............................................ 2.5W (25 MHz) 2.7 DC Characteristics ...
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AC Specifications This section describes the AC specifications for the 80960KB pins. All input and output timings are specified relative to the 1.5 V level of the rising edge of CLK2. For output timings the specifications refer to ...
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AC Specification Tables Table 7. 80960KB AC Characteristics (16 MHz) Symbol Parameter T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time (CLK2 Processor Clock Fall Time (CLK2) 4 ...
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Table 8. 80960KB AC Characteristics (20 MHz) Symbol Parameter T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time (CLK2 Processor Clock Fall Time (CLK2 Processor Clock ...
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Table 9. 80960KB AC Characteristics (25 MHz) Symbol Parameter T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time (CLK2 Processor Clock Fall Time (CLK2 Processor Clock Rise ...
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HIGH LEVEL (MIN) 0.55V CC LOW LEVEL (MAX) 0. Figure 15. Processor Clock Pulse (CLK2) CLK2 CLK RESET OUTPUTS INIT PARAMETERS (BADAC, INT /IAC) MUST BE SET UP 8 CLOCKS 0 PRIOR TO THIS CLK2 EDGE INIT ...
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... This package uses fine-pitch gull wing leads arranged in a single row along the package perimeter with 0.025 inch (0.64 mm) spacing (see Figure 20). Dimensions for both package types are given in the Intel Packaging handbook (Order #240800 ...
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P V N.C. N.C. N. N.C. N. DEN N. FAIL DT ...
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N.C. N. N.C. N.C. N.C. N.C. M N.C. N.C. N. N.C. N. N.C. N. N.C. N.C. N.C. H N.C. N.C. N.C. ...
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LAD0 LAD1 101 LAD2 102 ...
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Pinout Table 10. 80960KB PGA Pinout — In Pin Order Pin Signal Pin LAD LAD LAD C10 16 A6 LAD C11 14 A7 LAD ...
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Table 11. 80960KB PGA Pinout — In Signal Order Signal Pin Signal ADS D2 LAD ALE D1 LAD BADAC C3 LAD BE H2 LAD LAD LAD LAD 3 CACHE F3 ...
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Table 12. 80960KB PQFP Pinout — In Pin Order Pin Signal Pin 1 HLDA 34 2 ALE LAD26 4 LAD27 37 5 LAD28 38 6 LAD29 39 7 LAD30 LAD31 9 42 VSS 10 ...
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Table 13. 80960KB PQFP Pinout — In Signal Order Signal Pin Signal ADS 132 LAD ALE 2 LAD BADAC 129 LAD BE 14 LAD LAD LAD LAD 3 CACHE 10 ...
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Package Thermal Specification The 80960KB is specified for operation when case temperature is within the range 0°C to 85°C (PGA) or 0°C to 100°C (PQFP). Measure case temperature at the top center of the package. Ambient temper- ature can ...
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Table 15. 80960KB PQFP Package Thermal Characteristics Parameter Junction-to-Case Case-to-Ambient (No Heatsink) NOTES: 1. This table applies to 80960KB PQFP soldered directly to board 18°C/W (approx 18°C/W (approx.) JB ...
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AIRFLOW (ft/min) PQFP PGA with no PGA with omni- heatsink directional heatsink Figure 23. 16 MHz Maximum Allowable Ambient Temperature ...
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PQFP Figure 25. 25 MHz Maximum Allowable Ambient Temperature 120 115 110 105 100 100 PGA with no heatsink Figure 26. Maximum Allowable Ambient Temperature ...
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WAVEFORMS Figures 27, 28, 29 and 30 show the waveforms for various transactions on the 80960KB’s local bus CLK2 CLK LAD31:0 ALE ADS BE3:0 W/R DT/R DEN READY Figure 27. Non-Burst Read and Write Transactions Without Wait ...
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CLK2 CLK LAD31:0 ALE ADS BE3:0 W/R DT/R DEN READY Figure 28. Burst Read and Write Transaction Without Wait States ...
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CLK2 CLK LAD31:0 ALE ADS BE3:0 W/R DT/R DEN READY Figure 29. Burst Write Transaction with Wait States 80960KB T T ...
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CLK2 CLK LAD31:0 ALE ADS BE3:2 BE1:0 W/R DT/R DEN READY Figure 30. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word Boundary ( Wait ...
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PREVIOUS INTERRUPT CYCLE ACKNOWLEDGEMENT CYCLE CLK2 CLK INTR LAD31:0 ADDR ALE ADS INTA DT/R DEN LOCK READY NOTE: INTR can go low no sooner than the input hold time following the ...
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... Redrawn for clarity. CLK signal drawn with more likely phase relationship to CLK2. Open-drain output signals drawn to show correct inactive states. -005 Deleted all references to 10 MHz. Intel no longer offers a 10 MHz 80960KB device. -006 DEN pin description omitted from revision -005. ...