A80960CA25 Intel, A80960CA25 Datasheet

A80960CA25

Manufacturer Part Number

A80960CA25

Description

IC MPU I960CA 25MHZ 168-PGA

Manufacturer

Intel

Datasheet

1.A80960CA25.pdf (68 pages)

Specifications of A80960CA25

Processor Type

i960

Features

CA suffix, 32-Bit with DMA, 1K Cache

Speed

25MHz

Voltage

Mounting Type

Surface Mount

Package / Case

168-PGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

802884

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

A80960CA25

Manufacturer:

MAXIM

Quantity:

180

Current page: 1 of 68
Download datasheet (941Kb)

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent

licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

32-bit Parallel Architecture

— Two Instructions/clock Execution

— Load/Store Architecture

— Sixteen 32-bit Global Registers

— Sixteen 32-bit Local Registers

— Manipulates 64-bit Bit Fields

— 11 Addressing Modes

— Full Parallel Fault Model

— Supervisor Protection Model

Fast Procedure Call/Return Model

— Full Procedure Call in 4 Clocks

On-Chip Register Cache

— Caches Registers on Call/Ret

— Minimum of 6 Frames Provided

— Up to 15 Programmable Frames

On-Chip Instruction Cache

— 1 Kbyte Two-Way Set Associative

— 128-bit Path to Instruction Sequencer

— Cache-Lock Modes

— Cache-Off Mode

High Bandwidth On-Chip Data RAM

— 1 Kbyte On-Chip Data RAM

— Sustains 128 bits per Clock Access

• Four 59 Mbytes/s DMA Channels with Data Chaining

• Demultiplexed 32-bit Burst Bus with Pipelining

• Two Instructions/Clock Sustained Execution

80960CA-33, -25, -16

November 1993

Four On-Chip DMA Channels

— 59 Mbytes/s Fly-by Transfers

— 32 Mbytes/s Two-Cycle Transfers

— Data Chaining

— Data Packing/Unpacking

— Programmable Priority Method

32-Bit Demultiplexed Burst Bus

— 128-bit Internal Data Paths to and

— Burst Bus for DRAM Interfacing

— Address Pipelining Option

— Fully Programmable Wait States

— Supports 8-, 16- or 32-bit Bus Widths

— Supports Unaligned Accesses

— Supervisor Protection Pin

Selectable Big or Little Endian Byte

Ordering

High-Speed Interrupt Controller

— Up to 248 External Interrupts

— 32 Fully Programmable Priorities

— Multi-mode 8-bit Interrupt Port

— Four Internal DMA Interrupts

— Separate, Non-maskable Interrupt Pin

— Context Switch in 750 ns Typical

from Registers

Order Number: 270727-006

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