A80960CF33 Intel, A80960CF33 Datasheet
A80960CF33
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A80960CF33 Summary of contents
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High-Performance Superscalar Embedded Microprocessor Product Features Socket and Object Code Compatible with 80960CA Two Instructions/Clock Sustained Execution Four 71 Mbytes/s DMA Channels with Data Chaining Demultiplexed 32-Bit Burst Bus with Pipelining 32-Bit Parallel Architecture — Two ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 Purpose .......................................................................................................................................... 7 2.0 80960CF Processor Overview ...................................................................................................... 7 2.1 The 80960C-Series Core ...................................................................................................... 8 2.2 Pipelined, Burst Bus ............................................................................................................. 9 2.3 Instruction Set Summary ...................................................................................................... 9 2.4 Flexible DMA Controller ........................................................................................................9 2.5 Priority Interrupt Controller.................................................................................................... 9 3.0 ...
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Contents 14 Bus Backoff (BOFF) Timings ...................................................................................................... 39 15 Relative Timings Waveforms ...................................................................................................... 39 16 Output Delay or Hold vs. Load Capacitance .............................................................................. 40 17 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC ................ 40 18 ...
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PQFP Package Thermal Characteristics ....................................................................24 13 Die Stepping Cross Reference ...................................................................................................25 14 Absolute Maximum Ratings ........................................................................................................26 15 Operating Conditions ..................................................................................................................26 16 D.C. Specifications .....................................................................................................................28 17 80960CF AC Characteristics (40 MHz) ......................................................................................29 18 80960CF AC Characteristics (33 MHz) ......................................................................................31 ...
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Contents This page intentionally left blank. 6 Datasheet ...
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... Purpose This document provides electrical characteristics of Intel’s i960 For functional descriptions consult the i960 number 270710). To obtain data sheet updates and errata, visit the Intel World Wide Web site at http://www.intel.com 2.0 80960CF Processor Overview Intel’s 80960CF is the second processor in the series of superscalar i960 microprocessors that also includes the 80960CA and the 80960HA/HD/HT ...
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... The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture. This core may sustain execution of two instructions per clock (80 MIPS at 40 MHz). To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the C-Series core implementation. Factors that contribute to the core’ ...
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Pipelined, Burst Bus A 32-bit high performance bus controller interfaces the 80960CF to external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at 40 MHz). Internally programmable wait states and ...
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... This section describes the pins, pinouts and thermal characteristics for the 80960CF in the 168-pin Ceramic Pin Grid Array (PGA) package; the 80960CF-33 and -25 devices are also available in the 196-pin Plastic Quad Flat Package (PQFP). For complete package specifications and information, see the Intel Packaging Databook, available in individual chapters, at http://www.intel.com. 10 Arithmetic ...
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Pin Descriptions This section defines the 80960CF pins. descriptions in Tables 3 through 5. processor control signals. Note: All pins float while the processor is in the ONCE mode. Table 2. Symbol Legend Symbol I Input only pin O ...
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Table 3. 80960CF Pin Description—External Bus Signals (Sheet Name Type O S A31:2 H(Z) R(Z) I/O S(L) D31:0 H(Z) R( BE3:0 H(Z) R( W/R H(Z) R( ADS H(Z) ...
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Table 3. 80960CF Pin Description—External Bus Signals (Sheet Name Type O S BLAST H(Z) R( DT/R H(Z) R( DEN H(Z) R( LOCK H(Z) R(1) I S(L) HOLD H(Z) R(Z) I S(L) ...
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Table 4. 80960CF Pin Description—Processor Control Signals (Sheet Name Type I A(L) RESET H(Z) R( FAIL H(Q) R(0) I S(L) STEST H(Z) R(Z) I A(L) ONCE H(Z) R(Z) I A(E) CLKIN H(Z) ...
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Table 4. 80960CF Pin Description—Processor Control Signals (Sheet Name Type O S PCLK2:1 H(Q) R(Q) V – – – CCPLL NC – Table 5. 80960CF Pin Description—DMA and Interrupt Unit Control Signals Name ...
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Mechanical Data 3.3.1 80960CF PGA Pinout Figure 2 shows the complete 80960CF PGA pinout as viewed from the top side of the component (i.e., pins facing down). pin-side of the package (i.e., pins facing up). ...
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Figure 3. 80960CF PGA Pinout—View from Bottom (Pins Facing Up BOFF D3 2 FAIL STEST ONCE DREQ0 NC 6 DREQ1 DREQ2 DREQ3 ...
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Table 6. 80960CF PGA Pinout—In Signal Order Address Bus Signal Pin A31 S15 A30 Q13 A29 R14 A28 Q14 A27 S16 A26 R15 A25 S17 A24 Q15 A23 R16 A22 R17 A21 Q16 A20 P15 A19 P16 ...
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Table 7. 80960CF PGA Pinout—In Pin Order Pin Signal FAIL DREQ1 A7 DREQ3 A8 DACK1 A9 DACK2 A10 DACK3 A11 EOP/TC0 A12 EOP/TC1 A13 EOP/TC2 A14 EOP/TC3 A15 XINT1 A16 ...
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PQFP Pinout (80960CF-33 and -25 Only) Table 8 and Table 9 80960CF PQFP pinout as viewed from the top side. See page 26 for specifications and recommended connections. Table 8. 80960CF PQFP Pinout—In Signal Order ...
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Table 9. 80960CF PQFP Pinout—In Pin Order (80960CF-33 and -25 Only) Pin Signal Pin D23 36 4 D22 37 5 D21 38 6 D20 D19 ...
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Figure 4. 80960CF PQFP Pinout—Top View (80960CF-33 and -25 Only) 99 147 148 3.4 Package Thermal Specifications The 80960CF is specified for operation when case temperature (T 0 °C–100 °C for 33 and 25 MHz, and 0 ...
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Figure 5. Measuring 80960CF PGA and PQFP Case Temperature Measure PGA temperature at center of top surface center of top surface Table 10. Maximum T at Various Airflows with Heatsink († without Heatsink (†) A ...
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Table 11. 80960CF PGA Package Thermal Characteristics Parameter Junction-to-Case (Case measured as shown in Figure 5.) Case-to-Ambient (No Heatsink) Case-to-Ambient (With Heatsink) (See Note 3.) NOTES: 1. This table applies to 80960CF PGA plugged into socket or ...
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Figure 6. Register g0 ASCII 00 DECIMAL MSB Table 13. Die Stepping Cross Reference g0 Least Significant Byte 3.6 Sources for Accessories The following is a list of suggested sources for 80960CF accessories. This is ...
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... Case Temperature Under Bias Supply Voltage wrt. V Voltage on Other Pins wrt. V Note: The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. ...
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Recommended Connections Power and ground connections must be made to multiple V 80960CF-based circuit board should include power (V distribution. Every V connected to the ground plane. Pins identified as ‘NC’ must not be connected in the system. Liberal ...
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Table 16. D.C. Specifications Symbol V Input Low IL V Input High Voltage for all pins except RESET IH V Output Low Voltage OL Output High Voltage Input Low Voltage for RESET ILR V ...
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A.C. Specifications Table 17. 80960CF AC Characteristics (40 MHz) (Sheet Symbol T CLKIN Frequency F CLKIN Period CLKIN Period Stability CS CLKIN High Time T CH CLKIN Low Time CLKIN ...
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Table 17. 80960CF AC Characteristics (40 MHz) (Sheet Symbol Input Hold T IH1 IH2 T IH3 T IH4 T A31:2 Valid to ADS Rising AVSH1 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 ...
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Table 18. 80960CF AC Characteristics (33 MHz) (Sheet Symbol T CLKIN Frequency F CLKIN Period CLKIN Period Stability CS CLKIN High Time T CH CLKIN Low Time CLKIN Rise Time CR ...
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Table 18. 80960CF AC Characteristics (33 MHz) (Sheet Symbol T A31:2 Valid to ADS Rising AVSH1 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS T AVSH2 Rising T A31:2 Valid to DEN Falling ...
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Table 19. 80960CF AC Characteristics (25 MHz) (Sheet Symbol T CLKIN Frequency F CLKIN Period CLKIN Period Stability CS CLKIN High Time T CH CLKIN Low Time CLKIN Rise Time CR ...
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Table 19. 80960CF AC Characteristics (25 MHz) (Sheet Symbol T A31:2 Valid to ADS Rising AVSH1 BE3:0, W/R, SUP, D/C, T AVSH2 DMA, DACK3:0 Valid to ADS Rising T A31:2 Valid to DEN Falling ...
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Table 19. 80960CF AC Characteristics (25 MHz) (Sheet Symbol NOTES: 1. 80960CF-25 only, per the conditions in Conditions. 2. See Section 4.5.2, A.C. Timing Waveforms 3. See Figure 16 for capacitive derating information for output delays and ...
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A.C. Timing Waveforms Figure 8. Input and Output Clocks Waveform CLKIN PCLK2:1 Figure 9. CLKIN Waveform 1 1 ...
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Figure 10. Output Delay and Float Waveform PCLK2:1 Outputs Outputs NOTES OUTPUT DELAY - Maximum output delay is referred to as Output Valid Delay ( output delay is referred to as Output Hold (T ...
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Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform PCLK2:1 NMI, XINT7:0 Figure 13. Hold Acknowledge Timings PCLK2:1 Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA HOLD HOLDA NOTES ...
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Figure 14. Bus Backoff (BOFF) Timings PCLK2:1 Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA BOFF Figure 15. Relative Timings Waveforms PCLK2:1 ADS A31:2, BE3:0, W/R, LOCK, SUP, D/C, DMA D31:0 WAIT DT/R DEN ...
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Derating Curves Figure 16. Output Delay or Hold vs. Load Capacitance nom + 10 nom + 5 nom 50 Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum V 0 ...
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Figure 19. I vs. Frequency and Temperature—80960CF-40 CC 1100 0 0 5.0 Reset, Backoff and Hold Acknowledge Table 20 lists the condition of each processor output pin while RESET is asserted (low). lists the condition of each processor output pin ...
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Table 20. Reset Conditions Pins State During Reset (HOLDA inactive) A31:2 Floating D31:0 Floating BE3:0 Driven high (Inactive) W/R Driven low (Read) ADS Driven high (Inactive) WAIT Driven high (Inactive) BLAST Driven low (Active) DT/R Driven low ...
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Bus Waveforms Figure 20. Cold Reset Waveform Datasheet 80960-40, -33, -25 43 ...
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PCLK2:1 ADS, LOCK, WAIT, DEN, DACK3:0 W/R, DT/R, BREQ, FAIL BLAST SUP, DMA, A31:2, D/C, BE3:0 D31:0, EOP/TC3:0 STEST Maximum Low to RESET 4 PCLK Periods RESET Minimum Tdelay 1PCLK Valid State RESET Tsetup Thold 1 PCLK 1 PCLK High ...
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CLKIN V CC PCLK2:1 ADS, BE3:0, A31:2, D31:0, LOCK, WAIT, BLAST,W/R, D/C, DEN, DT/R, HOLD, HOLDA, BLAST, FAIL, SUP,BREQ, 3:0 DMA, EOP /TC3:0, STEST, XINT7:0, NMI, DACK3:0, DREQ3:0 READY, BTERM RESET ONCE CLKIN and V RESET high, minimum 32 CLKIN ...
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Figure 23. Clock Synchronization in the 2-x Clock Mode CLKIN RESET PCLK2:1 (Case 1) PCLK2:1 (Case 2) Note: Case 1 and Case 2 show two possible polarities of PCLK2:1 Figure 24. Clock Synchronization in the 1-x Clock ...
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Figure 25. Non-Burst, Non-Pipelined Requests Without Wait States Byte Function Order Bit 31- Value 0..0 x PCLK ADS A31:4, SUP , DMA, D/C, BE3:0, LOCK BLAST DEN A3:2 WAIT D31:0 Datasheet ...
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Figure 26. Non-Burst, Non-Pipelined Read Request With Wait States Function Order Bit 31-23 0 Value 0..0 PCLK ADS A31:2, BE3:0 W/R BLAST DT/R DEN DMA, D/C, SUP, LOCK WAIT D31:0 48 Byte Bus Width ...
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Figure 27. Non-Burst, Non-Pipelined Write Request With Wait States Function Bit 31-23 0 Value 0..0 PCLK ADS A31:2, BE3:0 W/R BLAST DT/R DEN SUP, DMA, D/C, LOCK WAIT D31:0 Datasheet Byte Bus Order Width WDD WAD 22 ...
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Figure 28. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus Function Bit 31-23 0 Value 0..0 PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK BLAST DEN A3:2 WAIT D31:0 50 ...
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Figure 29. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus Function Bit 31-23 0 Value 0..0 PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 Datasheet Byte Bus Order Width ...
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Figure 30. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus Function Bit 31-23 0 Value 0..0 PCLK ADS A31:4, SUP DMA, D/C, BE3:0, LOCK BLAST DEN A3:2 WAIT D31:0 52 ...
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Figure 31. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus Byte Function Order Bit 31-23 0 Value 0..0 PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 Datasheet Bus Width ...
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Figure 32. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus Function Order Bit 31-23 0 Value 0..0 PCLK ADS SUP, DMA, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE W/R BLAST DT/R DEN A3:2 BE1/A1 WAIT D31:0 54 Byte ...
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Figure 33. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus Byte Function Order Bit 31-23 0 Value 0..0 PCLK ADS SUP, DMA, D/C, LOCK, A31:4 W/R BLAST DT/R DEN A3:2 BE1/A1, BE0/A0 WAIT D31:0 Datasheet Bus ...
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Figure 34. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus Function Bit 31-23 0 Value 0..0 PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R A3:2 BE3:0 D31:0 WAIT BLAST DT/R DEN 56 Byte Bus N N ...
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Figure 35. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus Byte Function Order Bit 22 31- Value 0..0 x PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R A3:2 BE3:0 D31:0 WAIT BLAST DT/R DEN Datasheet Bus N ...
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Figure 36. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus Byte Function Order Bit 31-23 0 Value 0..0 PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R A3:2 D31:0 WAIT BLAST DT/R DEN 58 Bus N ...
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Figure 37. Burst, Pipelined Read Request With Wait States, 32-Bit Bus Byte Function Order Bit 31-23 0 Value 0..0 PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R A3:2 D31:0 WAIT BLAST DT/R DEN Datasheet Bus Width ...
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Figure 38. Burst, Pipelined Read Request With Wait States, 16-Bit Bus Function Bit 31-23 0 Value 0..0 PCLK ADS A31:4, SUP, DMA, D/C, BE0/BLE, BE3/BHE, LOCK W/R A3:2 BE1 /A1 D31:0 WAIT BLAST DT/R DEN 60 Byte ...
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Figure 39. Burst, Pipelined Read Request With Wait States, 8-Bit Bus Byte Function Order Bit 22 31- Value 0..0 x PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R A3:2 BE1/A1, BE0/A0 D31:0 WAIT BLAST DT/R DEN Datasheet Bus ...
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Figure 40. Using External READY PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 WAIT D31:0 62 Quad-Word Read Request RAD ...
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Figure 41. Terminating a Burst with BTERM PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 WAIT D31:0 Note: READY adds memory access time to data transfers, whether or not the bus access ...
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Figure 42. BOFF Functional Timing ADS BLAST READY BOFF A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R D31:0, (WRITES) Note: READY/BTERM must be enabled BURST NON-BURST MAY CHANGE SUSPEND REQUEST Begin Request BOFF may be ...
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Figure 43. HOLD Functional Timing PCLK2:1 ADS A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R BLAST HOLD HOLDA Datasheet Word Read Word Read Request Request Hold State RAD RAD XDA N XDA Valid 80960-40, -33, ...
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Figure 44. DREQ and DACK Functional Timing PCLK2:1 ADS BLAST ! ( READY & !WAIT & ) DACKx (All Modes) DREQx (Case 1) DREQx (Case 2) Note: 1. Case 1: DREQ must deassert before DACK deasserts. This ...
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Figure 46. Terminal Count Functional Timing PCLK2:1 DREQ ADS DACK TC Note: Terminal Count becomes active during the last bus request of a buffer transfer. When the last LOAD/STORE bus request is executed as multiple bus accesses, the TC may ...
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Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions Byte Offset 0 Word Offset 0 Short-Word Load/Store Word Load/Store Double-Word Load/Store Short Request (Aligned) Byte, Byte ...
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Figure 49. A Summary of Aligned and Unaligned Transfers for Little Endian Regions 0 Byte Offset 0 Word Offset Triple-Word Load/Store Quad-Word Load/Store Datasheet One Three-Word Request (Aligned) Byte, Short, Word, Word, ...
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Figure 50. Idle Bus Operation PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0 LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 READY, BTERM 70 Write Request Idle Bus N = (not in Hold Acknowledge ...