MPC852TVR66 Freescale Semiconductor, MPC852TVR66 Datasheet

IC MPU POWERQUICC 66MHZ 256-PBGA

MPC852TVR66

Manufacturer Part Number
MPC852TVR66
Description
IC MPU POWERQUICC 66MHZ 256-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC852TVR66

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
66MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

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Freescale Semiconductor
Technical Data
MPC852T
Hardware Specifications
This document contains detailed information for the MPC852T
about power considerations, DC/AC electrical characteristics, AC
timing specifications, and pertinent electrical and physical
characteristics of the MPC852T. For information about functional
characteristics of the processor, refer to the MPC866
PowerQUICC Family Users Manual (MPC866UM). The
MPC852T contains a PowerPC
1 Overview
The MPC852T PowerQUICC
the MPC860 PowerQUICC family, and can operate up to 100
MHz on the MPC8xx core with a 66-MHz external bus. The
MPC852T has a 1.8 V core and a 3.3 V I/O operation with 5-V
TTL compatibility. The MPC852T integrated communications
controller is a versatile one-chip integrated microprocessor and
peripheral combination that can be used in a variety of controller
applications. It particularly excels in Ethernet control applications,
including CPE equipment, Ethernet routers and hubs, VoIP clients,
and WiFi access points.
The MPC852T is a PowerPC architecture-based derivative of the
Motorola MPC860 Quad Integrated Communications Controller
(PowerQUICC). The CPU on the MPC852T is the MPC8xx core,
a 32-bit microprocessor that implements the PowerPC
architecture, incorporating memory management units (MMUs)
and instruction and data caches. The MPC852T is the subset of
this family of devices.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
TM
TM
is a 0.18-micron derivative of
processor core.
10. Mandatory Reset Configurations . . . . . . . . . . . . . . . 11
11. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
13. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41
14. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43
15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 56
16. Mechanical Data and Ordering Information . . . . . . . 60
17. Document Revision History . . . . . . . . . . . . . . . . . . . 78
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 5
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 5
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7. Thermal Calculation and Measurement . . . . . . . . . . . 8
8. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9. Power Supply and Power Sequencing . . . . . . . . . . . 10
Contents
Rev. 3.1, 01/2005
MPC852TEC

Related parts for MPC852TVR66

MPC852TVR66 Summary of contents

Page 1

... The CPU on the MPC852T is the MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices. © Freescale Semiconductor, Inc., 2004. All rights reserved. processor core. MPC852TEC Rev. 3.1, 01/2005 Contents 1 ...

Page 2

... Fast Ethernet Controller (FEC) • General-purpose timers — Two 16-bit timers or one 32-bit timer — Gate mode can enable or disable counting. — Interrupt can be masked on reference match and event capture. 2 MPC852T Hardware Specifications, Rev. 3.1 Figure 1 shows the MPC852T block Freescale Semiconductor ...

Page 3

... One SPI (serial peripheral interface) — Supports master and slave modes — Supports multimaster operation on the same bus • PCMCIA interface — Master (socket) interface, release 2.1 compliant Freescale Semiconductor GRACEFUL STOP TRANSMIT MPC852T Hardware Specifications, Rev. 3.1 Features , , and ENTER HUNT MODE ...

Page 4

... Figure 1. MPC852T Block Diagram MPC852T Hardware Specifications, Rev. 3.1 Table 5 for a listing of the 5-V System Interface Unit (SIU) Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface 8-Kbyte 1 Virtual IDMA & 8 Serial DMA Channels SMC1 SPI Freescale Semiconductor ...

Page 5

... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND Thermal Characteristics Table 3 shows the thermal characteristics for the MPC852T. Freescale Semiconductor Table 1. Maximum Tolerated Ratings Symbol V (core – 0.3 to 3.4 ...

Page 6

... Table 4. Power Dissipation (P Frequency Bus Mode (MHz 2:1 100 MPC852T Hardware Specifications, Rev. 3.1 Symbol Value Unit °C/W θ θJMA θJMA θJMA R 24 θ θJC Ψ Ψ Typical Maximum Unit 110 140 mW 150 180 mW 140 160 mW 170 200 mW 210 250 mW Freescale Semiconductor ...

Page 7

... TMS, TRST, DSCK and DSDI pins) for 5-V tolerant pins Input leakage current, Vin = V (Except TMS, TRST, DSCK, and DSDI) Input leakage current, Vin = 0 V (Except TMS, TRST, DSCK and DSDI pins) 2 Input capacitance Freescale Semiconductor and 1.9 V. and V DDL DDSYN NOTE Table 4 represent V ...

Page 8

... P = power dissipation in package D 8 Symbol VOH VOL x IDDL where P DDL I/O I/O NOTE , in °C can be obtained from the equation: J MPC852T Hardware Specifications, Rev. 3.1 Min Max Unit 2.4 — V — 0 the power dissipation of the I/O drivers. Freescale Semiconductor ...

Page 9

... When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2 more accurate and complex model of the package can be used in the thermal simulation. Freescale Semiconductor . For instance, the user can change the air flow around the device, add a θCA MPC852T Hardware Specifications, Rev ...

Page 10

... V-tolerant pins can not exceed 5.5 V, and remaining input pins cannot exceed 3.465 V. This restriction applies to power-on reset or power down and normal operation that operates at a lower voltage than the I/O voltage V and V (GND). DDH SS MPC852T Hardware Specifications, Rev. 3.1 . The I/O section of DDH . In DDH Freescale Semiconductor ...

Page 11

... SIUMCR[DBGC] should be programmed with the same value in the boot code after reset. If hardware reset configuration word (HRCW) is disabled, by negating the RSTCONF during the HRESET assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset. Freescale Semiconductor during power-on reset or power down. must not exceed 3.465. ...

Page 12

... PBPAR[14] PBPAR[16-23] PBPAR[26-27] PBDIR[14] PBDIR[16-23] PBDIR[26-27] PCPAR[8-11] PCDIR[14] PCDIR[8-11] PCDIR[14] and GND should be kept to less than half an inch per capacitor lead and GND planes should be used. DD MPC852T Hardware Specifications, Rev. 3.1 Value (binary and GND circuits. Pull up all unused DD Freescale Semiconductor ...

Page 13

... CLKOUT. For a non-integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew. B1b CLKOUT frequency jitter peak-to-peak B1c Frequency jitter on EXTCLK Freescale Semiconductor ).” Table 7 Part 50MHz Freq Min Max Min ...

Page 14

... Freescale Semiconductor Unit Max 9.1 ns 9.1 ns 4.00 ns 4.00 ns — ns — ns — ns 10.00 ns 10.00 ns 10. ...

Page 15

... B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375 6.6) B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0 (MAX = 0. 8.00) Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz Min Max Min 2.50 15.00 2 ...

Page 16

... Freescale Semiconductor Unit Max — ns — ns 9.00 ns 9.00 ns — ns — ns 9.00 ns 10.50 ns 10.50 ns 12.30 ns 12.30 ns — ...

Page 17

... B30b WE(0:3)/BS_B[0:3] negated to A(0:31) Invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN = 1. 2.00) Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz Min Max Min 5.60 — ...

Page 18

... Freescale Semiconductor Unit Max — ns — ns 6.00 ns 10.50 ns 8.00 ns 10.00 ns 12.30 ns 6.00 ns 10.50 ns 8.00 ns 10.50 ns ...

Page 19

... GxT4 in the corresponding word in the UPM (MIN = 0. 2.00) B37 UPWAIT valid to CLKOUT falling edge = 0. 6.00) B38 CLKOUT falling edge to UPWAIT valid = 0. 1.00) Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz Min Max Min 13.30 18.00 11.30 1.50 6 ...

Page 20

... MPC852T Hardware Specifications, Rev. 3.1 40 MHz 50 MHz 66 MHz Max Min Max Min — 7.00 — 7.00 — 7.00 — 7.00 — 7.00 — 7.00 — 2.00 — 2.00 — TBD — TBD — Figure 18. Freescale Semiconductor Unit Max — ns — ns — ns — ns TBD ns ...

Page 21

... Inputs Inputs A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification Figure 4 provides the timing for the external clock. CLKOUT Freescale Semiconductor 0 2.0 V 2.0 V 0 2.0 V 2.0 V 0.8 V 0.8 V ...

Page 22

... CLKOUT TS, BB TA, BI TEA Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing B8a B9 B8b B11 B12 B11a B12a B14 B15 MPC852T Hardware Specifications, Rev. 3.1 B13 B13a Freescale Semiconductor ...

Page 23

... BB, BG, BR Figure 7. Synchronous Input Signals Timing Figure 8 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT TA D[0:31], DP[0:3] Freescale Semiconductor B16 B17 B16a B17a B16b B17 B16 B17 B18 B19 Figure 8 ...

Page 24

... GPCM factors control. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 10. External Bus Read Timing (GPCM Controlled—ACS = 00) 24 B20 B21 B11 B12 B8 B22 B25 B28 B18 MPC852T Hardware Specifications, Rev. 3.1 B23 B26 B19 Freescale Semiconductor ...

Page 25

... A[0:31] CSx OE D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) Freescale Semiconductor B11 B12 B8 B22a B24 B25 B18 B11 B12 B8 B22b B22c B24a B25 B18 MPC852T Hardware Specifications, Rev ...

Page 26

... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) 26 B12 B8 B22a B27 B27a B22b B22c MPC852T Hardware Specifications, Rev. 3.1 B23 B26 B18 B19 Freescale Semiconductor ...

Page 27

... GPCM factors control. CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] OE D[0:31], DP[0:3] Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 0) Freescale Semiconductor B12 B25 B26 B8 MPC852T Hardware Specifications, Rev. 3.1 Bus Signal Timing B30 B23 B28 B29b B29 B9 ...

Page 28

... Bus Signal Timing CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) 28 B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 MPC852T Hardware Specifications, Rev. 3.1 B30a B30c B23 B29c B29g B29a B29f B9 Freescale Semiconductor ...

Page 29

... CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) Freescale Semiconductor B12 B8 B22 B25 B26 B8 MPC852T Hardware Specifications, Rev. 3.1 Bus Signal Timing B30b B30d B28b B28d B23 B29e B29i B29d B29h B29b B28a B28c ...

Page 30

... UPM controls. CLKOUT B8 A[0:31] CSx BS_A[0:3] B35 GPL_A[0:5], GPL_B[0:5] Figure 17. External Bus Timing (UPM Controlled Signals) 30 B31a B31d B31 B34 B34a B34b B32a B32d B32 B36 B35a B35b B33 MPC852T Hardware Specifications, Rev. 3.1 B31c B31b B32c B32b B33a Freescale Semiconductor ...

Page 31

... UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Freescale Semiconductor B38 B38 MPC852T Hardware Specifications, Rev. 3.1 Bus Signal Timing 31 ...

Page 32

... Figure 21. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 22 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 22. Asynchronous External Master—Control Signals Negation Timing 32 B41 B42 B40 B39 B40 B43 MPC852T Hardware Specifications, Rev. 3.1 B22 B22 Freescale Semiconductor ...

Page 33

... Figure 23. Interrupt Detection Timing for External Level Sensitive Lines Figure 24 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT IRQx Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines Freescale Semiconductor Table 10. Interrupt Timing All Frequencies 1 Characteristic 4xT CLOCKOUT ...

Page 34

... Freescale Semiconductor Unit ...

Page 35

... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 25. PCMCIA Access Cycles Timing External Bus Read Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 B18 MPC852T Hardware Specifications, Rev. 3.1 ...

Page 36

... Figure 26. PCMCIA Access Cycles Timing External Bus Write Figure 27 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITA Figure 27. PCMCIA WAIT Signals Detection Timing 36 P44 P46 P45 P48 P50 P52 P53 B8 P55 P56 MPC852T Hardware Specifications, Rev. 3.1 P47 P49 P51 P54 P52 B9 Freescale Semiconductor ...

Page 37

... PCMCIA output port timing for the MPC852T. CLKOUT Output Signals HRESET OP2, OP3 Figure 29 provides the PCMCIA output port timing for the MPC852T. CLKOUT Input Signals Freescale Semiconductor Table 12. PCMCIA Port Timing 33 MHz Min Max Min — 19.00 — 1 (MIN = 0.75 x 25.70 — ...

Page 38

... Figure 30. Debug Port Clock Input Timing D64 D65 D66 D67 Figure 31. Debug Port Timings MPC852T Hardware Specifications, Rev. 3.1 All Frequencies Unit Min Max — — CLOCKOUT — — CLOCKOUT 0.00 3.00 ns 8.00 — ns 5.00 — ns 0.00 15.00 ns 0.00 2.00 ns D62 D63 Freescale Semiconductor ...

Page 39

... B1 + 25.00) J93 DSDI, DSCK set up (MIN = 3.00 x B1) J94 DSDI, DSCK hold time (MIN = 0. 0.00) SRESET negated to CLKOUT rising edge for J95 DSDI and DSCK sample (MIN = 8.00 x B1) Freescale Semiconductor Table 14. Reset Timing 33 MHz 40 MHz Min Max Min — ...

Page 40

... CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 33. Reset Timing—Data Bus Weak Drive during Configuration 40 R71 R76 R73 R74 R75 R69 R79 R77 R78 MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor ...

Page 41

... TCK falling edge to output valid out of high impedance J94 TCK falling edge to output high impedance J95 Boundary scan input valid to TCK rising edge J96 TCK rising edge to boundary scan input invalid Freescale Semiconductor R70 R82 R80 R80 R81 Figure 35 Table 15. JTAG Timing Characteristic MPC852T Hardware Specifications, Rev ...

Page 42

... TMS, TDI TDO Figure 36. JTAG Test Access Port Timing Diagram TCK TRST 42 J82 J83 J82 Figure 35. JTAG Test Clock Input Timing J85 J86 J87 J88 J91 J90 Figure 37. JTAG TRST Timing Diagram MPC852T Hardware Specifications, Rev. 3.1 J83 J84 J89 Freescale Semiconductor ...

Page 43

... Port C interrupt pulse width low (edge-triggered mode) 36 Port C interrupt minimum time between active edges Figure 39 shows the port C interrupt detection timing. Port C (Input) Freescale Semiconductor J92 J93 Table 16. Port C Interrupt Timing Characteristic 35 Figure 39. Port C Interrupt Detection Timing MPC852T Hardware Specifications, Rev. 3.1 ...

Page 44

... Applies to high-to-low mode (EDM=1) CLKO (Output) DREQ (Input) Figure 40. IDMA External Requests Timing Diagram 44 Figure 40 Table 17. IDMA Controller Timing Characteristic 1 40 MPC852T Hardware Specifications, Rev. 3.1 through Figure 43. All Frequencies Min Max 7 — 3 — — 12 — 12 — 20 — — 41 Freescale Semiconductor Unit ...

Page 45

... CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 41. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 42. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA Freescale Semiconductor MPC852T Hardware Specifications, Rev. 3.1 CPM Electrical Characteristics 45 ...

Page 46

... Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle 50 BRGOX Figure 44. Baud Rate Generator Timing Diagram 46 42 Figure 44. Table 18. Baud Rate Generator Timing All Frequencies Characteristic MPC852T Hardware Specifications, Rev. 3.1 45 Unit Min Max — — ns Freescale Semiconductor ...

Page 47

... RCLK3 and TCLK3 width low 102 RCLK3 and TCLK3 rise/fall time 103 TXD3 active delay (from TCLK3 falling edge) 104 RTS3 active/inactive delay (from TCLK3 falling edge) 105 CTS3 setup time to TCLK3 rising edge Freescale Semiconductor Figure Table 19. Timer Timing All Frequencies Characteristic Table 20 ...

Page 48

... MPC852T Hardware Specifications, Rev. 3.1 All Frequencies Unit Min Max 5.00 — ns 5.00 — ns 5.00 — ns All Frequencies Unit Min Max 0.00 SYNCCLK/3 MHz — — ns 0.00 30.00 ns 0.00 30.00 ns 40.00 — ns 40.00 — ns 0.00 — ns 40.00 — ns Freescale Semiconductor ...

Page 49

... Figure 46. SCC NMSI Receive Timing Diagram TCLK3 102 TxD3 (Output) RTS3 (Output) CTS3 (Input) CTS3 (SYNC Input) Figure 47. SCC NMSI Transmit Timing Diagram Freescale Semiconductor 102 101 100 107 102 101 100 103 105 104 MPC852T Hardware Specifications, Rev. 3.1 CPM Electrical Characteristics ...

Page 50

... Figure 48. HDLC Bus Timing Diagram Figure 49 through Table 22. Ethernet Timing Characteristic 1 1 MPC852T Hardware Specifications, Rev. 3.1 104 Figure 53. All Frequencies Unit Min Max 40 — ns — — 120 ns 20 — — — ns 100 — ns — — 101 ns — 6 Freescale Semiconductor ...

Page 51

... SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) Figure 49. Ethernet Collision Timing Diagram RCLK3 RxD3 (Input) RENA(CD3) (Input) Figure 50. Ethernet Receive Timing Diagram Freescale Semiconductor Table 22. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 MPC852T Hardware Specifications, Rev. 3.1 ...

Page 52

... Figure 51. Ethernet Transmit Timing Diagram RCLK3 RxD3 0 (Input) Start Frame De- RSTRT (Output) Figure 52. CAM Interface Receive Start Timing Diagram REJECT Figure 53. CAM Interface REJECT Timing Diagram 52 128 121 132 1 1 BIT1 125 137 MPC852T Hardware Specifications, Rev. 3.1 129 134 BIT2 136 Freescale Semiconductor ...

Page 53

... SPICLK (CI=1) (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 54. SPI Master ( Timing Diagram Freescale Semiconductor Figure 54 and Figure Table 23. SPI Master Timing Characteristic 167 166 160 167 166 Data lsb 165 164 166 Data lsb MPC852T Hardware Specifications, Rev ...

Page 54

... Data lsb 165 164 Data Figure 56 and Figure Table 24. SPI Slave Timing Characteristic MPC852T Hardware Specifications, Rev. 3.1 msb 166 lsb msb 57. All Frequencies Unit Min Max 2 — t cyc 15 — — — t cyc 1 — t cyc 20 — — ns — Freescale Semiconductor ...

Page 55

... SPICLK (CI=1) (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 56. SPI Slave ( Timing Diagram Freescale Semiconductor 172 182 181 170 181 182 180 Data lsb 179 181 182 Data lsb MPC852T Hardware Specifications, Rev. 3.1 ...

Page 56

... Data 179 176 181 182 msb Data Table 25. MII Receive Signal Timing Characteristic MPC852T Hardware Specifications, Rev. 3.1 174 178 lsb lsb Min Max Unit 5 — — ns 35% 65% MII_RX_CLK period 35% 65% MII_RX_CLK period Freescale Semiconductor msb msb ...

Page 57

... MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid M7 MII_TX_CLK pulse width high M8 MII_TX_CLK pulse width low Figure 59 shows the MII transmit signal timing diagram. Freescale Semiconductor Table 26. MII Transmit Signal Timing Characteristic MPC852T Hardware Specifications, Rev. 3.1 FEC Electrical Characteristics ...

Page 58

... MII_MDIO (input) to MII_MDC rising edge hold Table 27. MII Async Inputs Signal Timing Characteristic M9 Figure 60. MII Async Inputs Timing Diagram Characteristic MPC852T Hardware Specifications, Rev. 3.1 Min Max Unit 1.5 — MII_TX_CLK period Min Max Unit 0 — ns — — — ns Freescale Semiconductor ...

Page 59

... M15 MII_MDC pulse width low Figure 61 shows the MII serial management channel timing diagram. MII_MDC (output) MII_MDIO (output) MII_MDIO (input) Figure 61. MII Serial Management Channel Timing Diagram Freescale Semiconductor Characteristic M14 MM15 M10 M11 M12 M13 MPC852T Hardware Specifications, Rev. 3.1 ...

Page 60

... The following sections give the pinout and pin listing for the JEDEC Compliant and the non-JEDEC versions of the PBGA package. 60 Temperature (Tj) Frequency (MHz) 0°C to 95° 100 – 40°C to 100°C 66 MPC852T Hardware Specifications, Rev. 3.1 Order Number MPC852TVR50 MPC852TZT50 MPC852TVR66 MPC852TZT66 MPC852TVR80 MPC852TZT80 MPC852TVR100 MPC852TZT100 TBD Freescale Semiconductor ...

Page 61

... XTAL EXTCLK WAIT_A VSSSYN PORST VDDSYN VSSSYN1 DP0 VDDL IP_A7 IP_A2 DP3 N/C IP_A0 IP_A4 DP2 Figure 62. Pinout of the PBGA Package - JEDEC Standard Freescale Semiconductor BS_A0 VDDL A28 A18 A23 A19 MII_CRS BS_A3 A22 A30 A29 A27 GPL_A0 WE1 BS_A2 A26 ...

Page 62

... Bidirectional Active Pull-up (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Input (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional (3.3V only) Freescale Semiconductor ...

Page 63

... UPWAITA C2 GPL_A4 GPL_A5 E4 PORESET P1 RSTCONF K4 HRESET J4 Freescale Semiconductor Pin Number MPC852T Hardware Specifications, Rev. 3.1 Mechanical Data and Ordering Information Type Bidirectional (3.3V only) Bidirectional Active Pull-up (3.3V only) Bidirectional (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) ...

Page 64

... Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Input (3.3V only) Bidirectional Three-state (3.3V only) Bidirectional (3.3V only) Bidirectional (3.3V only) Output Bidirectional (3.3V only) Bidirectional (3.3V only) Output Output Input (3.3V only) Bidirectional (Optional: Open-drain) (5V tolerant) Freescale Semiconductor ...

Page 65

... D15 SPIMOSI PB28 G13 SPIMISO BRGO4 PB25 H14 SMTXD1 PB24 H16 SMRXD1 PB15 L16 BRGO3 Freescale Semiconductor Pin Number MPC852T Hardware Specifications, Rev. 3.1 Mechanical Data and Ordering Information Type Bidirectional (5V tolerant) Bidirectional (Optional: Open-drain) (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional ...

Page 66

... Pin Number MPC852T Hardware Specifications, Rev. 3.1 Type Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Bidirectional (5V tolerant) Freescale Semiconductor ...

Page 67

... VDDH F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12, K5, K12, L5, L6, L7, L8, L9, L10, L11, L12 N/C A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16 Freescale Semiconductor Pin Number MPC852T Hardware Specifications, Rev. 3.1 Mechanical Data and Ordering Information Type Bidirectional ...

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... MDIO DDL J TCK PB25 PA10 PB24 K PC5 PC7 PA8 PA9 L PD13 PA2 PC6 PA3 V DDH M N/C PC4 PA1 PB15 N PD3 PD8 PD15 V PA0 DDL P IRQ7 PD6 PD9 PD12 PD14 R D12 IRQ0 PD4 N/C PD11 T D13 D0 PD5 PD10 N MII_TXEN PD7 N Freescale Semiconductor ...

Page 69

... T12, T7, R7, U6, T6 DP0 R5 IRQ3 DP1 R6 IRQ4 DP2 U5 IRQ5 DP3 T5 IRQ6 Freescale Semiconductor Table 31. Pin Assignments - non-JEDEC Pin Number MPC852T Hardware Specifications, Rev. 3.1 Mechanical Data and Ordering Information Type Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3 ...

Page 70

... Bidirectional (3.3 V only) Bidirectional (3.3 V only) Bidirectional Active Pull-up (3.3 V only) Bidirectional (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Output Output Output Output Output Output Output Output Output Output Output Bidirectional (3.3 V only) Output Input (3.3 V only) Freescale Semiconductor ...

Page 71

... OP2 L4 MODCK1 STS OP3 M2 MODCK2 DSDO BADDR[28:29] M4, M3 BADDR30 K4 REG Freescale Semiconductor Pin Number MPC852T Hardware Specifications, Rev. 3.1 Mechanical Data and Ordering Information Type Input (3.3 V only) Open-drain Open-drain Analog Output Analog Input (3.3 V only) Output Input (3.3 V only) Output ...

Page 72

... Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Freescale Semiconductor ...

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... PD13 L14 MII_RXD1 PD12 P16 MII_MDC PD11 R17 RXD3 MII_TX_ER PD10 T16 TXD3 MII_RXD0 Freescale Semiconductor Pin Number MPC852T Hardware Specifications, Rev. 3.1 Mechanical Data and Ordering Information Type Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (Optional: Open-drain) (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) ...

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... Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Bidirectional (5 V-tolerant) Input (5 V-tolerant) Input (5 V-tolerant) Input (5 V-tolerant) Input (5 V-tolerant) Output (5 V-tolerant) Input Bidirectional (5 V-tolerant) Output (5 V-tolerant) Input PLL analog GND PLL analog GND PLL analog V DD Freescale Semiconductor ...

Page 75

... G6, G7, G8, G9, G10, G11, G12, G13, H6, H13, J6, J13, K6, K13, DDH L6, L13, M6, M7, M8, M9, M10, M11, M12, M13 N/C B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17 Freescale Semiconductor Pin Number MPC852T Hardware Specifications, Rev. 3.1 Mechanical Data and Ordering Information Type ...

Page 76

... For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, refer to Plastic Ball Grid Array Application Note (order number: AN1231/D) that is available from your local Motorola sales office. 76 Figure 64 shows the mechanical dimensions of the PBGA package. MPC852T Hardware Specifications, Rev. 3.1 Freescale Semiconductor ...

Page 77

... Datum A, the seating plane, is defined by the spherical crowns of the solder balls. Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC852TVRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC852TZTXXX. Figure 64. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package Freescale Semiconductor MPC852T Hardware Specifications, Rev. 3.1 Mechanical Data and Ordering Information 77 ...

Page 78

... Added subscripts to timing diagrams for B1-B35, to specify memory controller settings for the specific edges. In Table 15-30, specified EXTCLK as 3.3 V. Added fast Ethernet controller to the features Added values for 80 and 100 MHz Initial release MPC852T Hardware Specifications, Rev. 3.1 , SSSYN1 Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK Freescale Semiconductor MPC852T Hardware Specifications, Rev. 3.1 Document Revision History 79 ...

Page 80

... All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical ...

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