MPC755BRX300LE Freescale Semiconductor, MPC755BRX300LE Datasheet

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... The MPC745 is identical to the MPC755 except it does not support the L2 cache interface. Figure 1 shows a block diagram of the MPC755. © Freescale Semiconductor, Inc., 2006. All rights reserved. 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Electrical and Thermal Characteristics . . . . . . . . . . . . 6 5 ...

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... Overview MPC755 RISC Microprocessor Hardware Specifications, Rev Figure 1. MPC755 Block Diagram Freescale Semiconductor ...

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... Support for IEEE standard 754 single- and double-precision floating-point arithmetic — Hardware support for divide — Hardware support for denormalized numbers — Single-entry reservation station — Supports non-IEEE mode for time-critical operations — Three-cycle latency, one-cycle throughput, single-precision multiply-add MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Features 3 ...

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... BurstRAMs (3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late write synchronous BurstRAMs — L2 configurable to cache, private memory, or split cache/private memory — Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported — 64-bit data bus MPC755 RISC Microprocessor Hardware Specifications, Rev Freescale Semiconductor ...

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... IEEE 1149.1 JTAG interface 3 General Parameters The following list provides a summary of the general parameters of the MPC755: Technology Die size Transistor count Logic design MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor virtual memory physical memory 0.22 µm CMOS, six-layer metal 6.61 mm × 7. ...

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... Table 1 provides the absolute 1 Maximum Value Unit –0.3 to 2.5 V –0.3 to 2.5 V –0.3 to 2.5 V –0.3 to 3.6 V –0.3 to 3.6 V –0 0 –0.3 to L2OV + 0 –0.3 to 3.6 V –55 to 150 °C /L2AV 3.3 V for 1.0 V for ms 0 Freescale Semiconductor Notes Figure 2. ...

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... Caution: The input threshold selection must agree with the OV Note: The input threshold settings above are different for all revisions prior to Rev. 2.8 (Rev. E). For more information, refer to Section 10.2, “Part Numbers Not Fully Addressed by This Document.” MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Not to Exceed 10% ...

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... L2OV 2.375 2.625 DD 3.135 3.465 V GND GND L2OV GND 105 j 1 400 MHz Unit Notes Min Max 1.90 2. 1.90 2. 1.90 2. 2.375 2.625 3.135 3.465 5 2.375 2.625 3.135 3.465 5 GND GND L2OV V DD GND 105 °C Section 10.2, “Part Freescale Semiconductor ...

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... See the MPC750 RISC Microprocessor Family User’s Manual for more information on the use of this feature. Specifications for the thermal sensor portion of the TAU are found in MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Table 4. Package Thermal Characteristics Symbol MPC755 ...

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... Min Max Unit 1.6 (L2) 2.0 (L2) –0.3 0.6 V –0.3 0 –0.3 0.4 V –0.3 0.4 V — 10 µA — 10 µA 1.7 — V 2.4 — V — 0.45 V — 0.4 V Freescale Semiconductor Notes Notes ...

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... Maximum power is measured at nominal V instructions which keep the execution units maximally busy. 3. Typical power is an average value measured at the nominal recommended V running a typical code sequence. 4. Not 100% tested. Characterized and periodically sampled. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Table 3) Nominal Bus Symbol ...

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... Section 4.2.1, “Clock AC Specifications,” Figure 3. 400 MHz Unit Max Min Max 350 200 400 MHz 700 400 800 MHz 100 25 100 MHz 2.0 — 2.0 ns 1.4 — 1 ±150 — ±150 ps μs 100 — 100 ,” for valid PLL_CFG[0:3] = 2.5 V). Freescale Semiconductor Notes ...

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... PLL division ratio selection to change. Both of these conditions are considered outside the specification and are not supported. Once HRESET is negated the states of the bus mode selection pins must remain stable. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor VM VM ...

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... MPC755. HRESET Mode Signals Figure 5 provides the AC test load for the MPC755. Output MPC755 RISC Microprocessor Hardware Specifications, Rev MVRH t MXRH VM = Midpoint Voltage (OV /2) DD Figure 4. Mode Input Timing Diagram = 50 Ω Figure 5. AC Test Load Ω Freescale Semiconductor ...

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... MCP and SRESET must be held asserted for a minimum of two bus clock cycles; INT and SMI should be held asserted until the exception is taken; CKSTP_IN must be held asserted until the system has been reset. See the MPC750 RISC Microprocessor Family User’s Manual for more information. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Table 3) Figure 6 ...

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... KHOV t KHOV t KHARP VM = Midpoint Voltage ( Figure 6. Input/Output Timing Diagram Figure Table 11 is specified by the maximum delay of the internal DLL. The Table 11 is the core frequency divided by one. Very few KHOZ t KHOZ t KHARPZ t KHOV t KHOX /2) in Table 11 provides the potential 7. Freescale Semiconductor ...

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... Backside L2 Timing Analysis for PCB Design Engineers. The L2CLK_OUTA and L2CLK_OUTB signals should not have more than two loads. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor are entirely independent of L2SYNC_IN closed loop system, where are referenced to this signal rather than the not-externally-visible Electrical and Thermal Characteristics Section 10 ...

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... AC timing and does not have to be considered in the L2 timing analysis. 7. Guaranteed by design. MPC755 RISC Microprocessor Hardware Specifications, Rev Table 3) Symbol f L2CLK t L2CLK t /t CHCL L2CLK t L2CSKW All Speed Grades Unit Notes Min Max 80 450 MHz 2.5 12 640 — L2CLK — — ±150 ps Freescale Semiconductor ...

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... All outputs when L2CR[14–15 All outputs when L2CR[14–15 Output hold times: All outputs when L2CR[14–15 All outputs when L2CR[14–15 All outputs when L2CR[14–15 All outputs when L2CR[14–15 MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Figure 7. t L2CLK t CHCL VM ...

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... MPC755 RISC Microprocessor Hardware Specifications, Rev Table 3) Symbol t L2CHOZ 8). Input timings are measured at the pins DVL2CH VM = Midpoint Voltage (L2OV Figure 8. L2 Bus Input Timing Diagrams All Speed Grades Unit Min Max ns — 2.4 — 2.6 — 2.8 — 3 L2CR L2CF t DXL2CH /2) DD Freescale Semiconductor Notes 3, 5 ...

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... L2 bus output timing diagrams for the MPC755. L2SYNC_IN All Outputs L2DATA BUS Figure 10 provides the AC test load for L2 interface of the MPC755. Output MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor L2CHOV t L2CHOX VM = Midpoint Voltage (L2OV Figure 9. L2 Bus Output Timing Diagrams = 50 Ω ...

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... JLDV t TDO JLOV Boundary-scan data t JLDH t TDO JLOH Boundary-scan data t JLDZ t TDO JLOZ = 50 Ω Figure 12 through 1 Min Max Unit 0 16 MHz 62.5 — — — — — IVJH 15 — — IXJH — — — — Figure Ω L Freescale Semiconductor Notes 11). ...

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... TRST timing diagram. VM TRST Figure 14 provides the boundary-scan timing diagram. VM TCK Boundary Data Inputs Boundary Data Outputs Boundary Data Outputs MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor JHJL t TCLK VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD Figure 13. TRST Timing Diagram ...

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... TCK VM TDI, TMS TDO TDO Figure 15. Test Access Port Timing Diagram MPC755 RISC Microprocessor Hardware Specifications, Rev IVJH t JLOV t JLOH Output Data Valid t JLOZ Output Data Valid VM = Midpoint Voltage ( IXJH Input Data Valid /2) Freescale Semiconductor ...

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... Part B shows the side profile of the PBGA package to indicate the direction of the top surface view. Part Part B Substrate Assembly Figure 16. Pinout of the MPC745, 255 PBGA Package as Viewed from the Top Surface MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Not to Scale View Encapsulant Pin Assignments Die 25 ...

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... Part B shows the side profile of the PBGA and CBGA package to indicate the direction of the top surface view. Part Part B Substrate Assembly Figure 17. Pinout of the MPC755, 360 PBGA and CBGA Packages as Viewed from the Top Surface MPC755 RISC Microprocessor Hardware Specifications, Rev Not to Scale View Encapsulant Die Freescale Semiconductor ...

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... C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12 HRESET A7 MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Pin Number Active Pinout Listings 1 I/O I/F Voltage ...

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... Low Input OV DD High Input OV DD Low I High Input OV DD High Input OV DD High Output OV DD Low Input OV DD Low Input OV DD High Input OV DD Low Input OV DD Low I High Output OV DD High I Low Output OV DD — — 2.0 V Freescale Semiconductor ...

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... DBDIS G1 DBG K1 DBWO D1 MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Pin Number ). These columns serve as a reference for the nominal voltage supported on a given DD Table 2 and the voltage supplied. For actual recommended value for proper operation of the processor interface. To allow for future I/O voltage changes, or GND ...

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... High Output L2OV DD — — 2.0 V Low Output L2OV DD — Output L2OV DD — Output L2OV DD High I/O L2OV DD High I/O L2OV DD — — L2OV DD — Input L2OV DD — Output L2OV DD High Input — High Input L2OV Low Output L2OV DD Freescale Semiconductor 2 2 ...

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... C8 TRST A10 TS K7 TSIZ[0:2] A9, B9, C9 TT[0:4] C10, D11, B12, C12, F11 G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 DD MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Pin Number Active K19 Pinout Listings 1 I/O I/F Voltage Notes High Output L2OV DD Low Input — ...

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... For actual recommended value for proper operation of the processor interface. To allow for future I/O voltage changes, or GND. DD for proper operation of the processor interface. To allow for future I/O voltage changes GND Active I/O I/F Voltage High Output L2OV DD for normal machine operation. Freescale Semiconductor Notes ...

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... 111213141516 e b 255X Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC745, MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor 21 × 255 (16 × 16 ball array – 1) 1.27 mm (50 mil) 2.25 mm 2.80 mm 0.75 mm (29.5 mil) 0.2 NOTES DIMENSIONING AND TOLERANCING 2 ...

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... TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY. Millimeters DIM Min Max A 2.65 3.20 A1 0.79 0.99 A2 1.10 1.30 A3 — 0.60 b 0.82 0.93 D 25.00 BSC D1 6.75 E 25.00 BSC 1.27 BSC Freescale Semiconductor ...

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... PBGA package CORNER 0 111213141516 B e 360X Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC755, MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor 25 × 360 (19 × 19 ball array – 1) 1.27 mm (50 mil) 2.22 mm 2.77 mm 0.75 mm (29.5 mil) 2X 0.2 A 0.2 C 171819 W V ...

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... Freescale Semiconductor Table 8. Bus 200 (400) 300 (600) 350 (700) 400 (800) — — — — — — — — — ...

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... Core Frequency (MHz) 250 266 275 300 325 333 350 366 MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Bus Bus VCO 33 MHz 50 MHz 66 MHz PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied PLL off, no core clocking occurs Table 17. Sample Core-to-L2 Frequencies ÷ ...

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... MPC755 also recommended that these decoupling , (L2)OV , and GND power planes in the PCB ÷2 ÷2.5 ÷3 150 125 160 133 for Figure 21 using surface mount capacitors DD pin, which is on the periphery of the 360 AV (or L2AV ) DD DD Freescale Semiconductor pin ...

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... When data is held high SW1 is closed (SW2 is open), and R becomes the resistance of the pull-up devices. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor planes, to enable quick recharging of the smaller chip capacitors even if the L2 interface of the MPC755 will not ...

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... equal to (L2)OV force (L2)OV DD OGND DD SW2 SW1 Figure 23. Data is held low, the is measured. force /2, is divided by the measured DD . Similarly, the impedance of the N /2, by the current sank DD /2. This method can be employed with )/ BGA Pin V force Freescale Semiconductor ...

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... If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Table 18. Impedance Characteristics ...

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... Berg header). The connector typically has pin 14 removed as a connector key. MPC755 RISC Microprocessor Hardware Specifications, Rev allows the COP port to independently assert HRESET or TRST, adds many benefits—breakpoints, watchpoints, register and memory Figure 24, if Freescale Semiconductor ...

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... HRESET from the target source to TRST of the part through a 0-Ω isolation resistor. 6. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown above. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor SRESET HRESET QACK ...

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... Figure 25. Package Exploded Cross-Sectional View with Several Heat Sink Options MPC755 RISC Microprocessor Hardware Specifications, Rev Figure is usually connected to the PCI bridge chip in a system and is an Heat Sink CBGA Package Heat Sink Clip Adhesive or Printed-Circuit Board 24; consequently, many different Option Freescale Semiconductor ...

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... Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor System Design Information 603-224-9988 408-749-7601 ...

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... Figure 27 describes the thermal performance of select thermal interface materials. MPC755 RISC Microprocessor Hardware Specifications, Rev Radiation Convection Heat Sink Printed-Circuit Board Radiation Convection Thermal Interface Material Die/Package Die Junction Package/Leads Freescale Semiconductor ...

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... Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01888-4014 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dow.com MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Contact Pressure (psi) ...

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... Assuming int ) of 5.0 W, the d ) × 5 versus airflow sa of 7°C/W, thus Freescale Semiconductor ) a ...

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... For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Thermalloy #2328B Pin-Fin Heat Sink (25 × 28 × 15 mm) 0 ...

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... Added Note 6 to Table 10; clarification only as this information is already documented in the MPC750 RISC Microprocessor Family User’s Manual. Revised Figure 24 and Section 1.8.7. Corrected Process Identifier for 450 MHz part in Table 20. Added XPC755BRXnnnTx series to Table 21. MPC755 RISC Microprocessor Hardware Specifications, Rev Table 19. Document Revision History Substantive Change(s) Table 7. Freescale Semiconductor ...

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... Corrected Note 6 of Table 9 to include TLBISYNC as a mode-select signal. Updated AC timing specifications in Table 10. Updated AC timing specifications in Table 12. Corrected AC timing specifications in Table 13. Added L1_TSTCLK, L2_TSTCLK, and LSSD_MODE pull-up requirements to Section 1.8.6. Corrected Figure 22. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Substantive Change( and L2AV DD DD Document Revision History ...

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... Removed log entries from Table 20 for revisions prior to public release. 0 — Product announced. Documentation made publicly available. MPC755 RISC Microprocessor Hardware Specifications, Rev Substantive Change(s) θ to Table 5. JA maximum for 1.8 V mode in Table 6. in Table 9, deleted Note 2 application note reference. and Min t values to Table 11. L2CLK Freescale Semiconductor ...

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... MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Section 10.2, “Part Numbers Not Fully lists the part numbers which do not fully conform to the specifications of Table 20 ...

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... L: 2.0 V ± 100 mV 0° to 105° PBGA RX = CBGA 450 T x Revision Level D: 2.7; PVR = 0008 3203 E: 2.8; PVR = 0008 3203 E: 2.8; PVR = 0008 3203 L D Revision Level D: 2.7; PVR = 0008 3203 L E Revision Level E: 2.8; PVR = 0008 3203 Freescale Semiconductor ...

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... MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Figure 29. 745 BGA Figure 29. Part Marking for BGA Device Ordering Information ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...