EE80C188XL12 Intel, EE80C188XL12 Datasheet - Page 47

• Manufacturer Part Number: EE80C188XL12
• Description: IC MPU 16BIT 5V 12MHZ 68PLCC
• Manufacturer: Intel

Specifications of EE80C188XL12

• Processor Type: 80C188
• Features: XL suffix, 16-Bit
• Speed: 12MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 864111

INSTRUCTION SET SUMMARY
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
The Effective Address (EA) of the memory operand
is computed according to the mod and r m fields
if mod
if mod
if mod
if mod
if r m
if r m
if r m
if r m
if r m
if r m
if r m
if r m
DISP follows 2nd byte of instruction (before data if
required)
disp-high disp-low
EA calculation time is 4 clock cycles for all modes
and is included in the execution times given whenev-
er appropriate
PROCESSOR CONTROL
CLC
CMC
STC
CLD
STD
CLI
STI
HLT
WAIT
LOCK
NOP
Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers
except if mod
e
e
e
e
e
e
e
e
e
e
Set interrupt
e
Clear interrupt
Set carry
Set direction
Halt
Clear carry
Clear direction
No Operation
Complement carry
Wait
Bus lock prefix
e
e
e
e
e
e
e
e
e
e
e
e
Function
Segment Override Prefix
0 0 1 reg 1 1 0
11 then r m is treated as a REG field
00 then DISP
high are absent
01 then DISP
tended to 16-bits disp-high is absent
10 then DISP
000 then EA
001 then EA
010 then EA
011 then EA
100 then EA
101 then EA
110 then EA
111 then EA
e
00 and r m
e
e
e
e
e
e
e
e
e
e
e
(TTT LLL are opcode to processor extension)
(BX)
(BX)
(BP)
(BP)
(SI)
(DI)
(BP)
(BX)
1 1 1 1 1 0 0 0
1 1 1 1 0 1 0 1
1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 0
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 0 1 0 0
1 0 0 1 1 0 1 1
1 1 1 1 0 0 0 0
1 0 0 1 0 0 0 0
0 disp-low and disp-
disp-low sign-ex-
disp-high disp-low
e
a
a
a
a
a
a
a
a
110 then EA
DISP
DISP
(SI)
(DI)
(SI)
(DI)
DISP
DISP
(Continued)
a
a
a
a
DISP
DISP
DISP
DISP
e
Format
reg is assigned according to the following
REG is assigned according to the following table
The physical addresses of all operands addressed
by the BP register are computed using the SS seg-
ment register The physical addresses of the desti-
nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment which may not be overridden
16-Bit (w
000 AX
001 CX
010 DX
011 BX
100 SP
101 BP
111 DI
110 SI
reg
00
01
10
11
e
1)
80C186XL
80C186XL 80C188XL
Cycles
Segment
Register
Clock
8-Bit (w
2
2
2
2
2
2
2
2
6
2
3
CS
DS
ES
SS
100 AH
101 CH
110 DH
111 BH
000 AL
001 CL
010 DL
011 BL
80C188XL
Cycles
Clock
2
2
2
2
2
2
2
2
6
2
3
e
0)
if TEST
Comments
e
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