IC MPU 16BIT 5V 20MHZ 68PLCC

EE80C188XL20

Manufacturer Part NumberEE80C188XL20
DescriptionIC MPU 16BIT 5V 20MHZ 68PLCC
ManufacturerIntel
EE80C188XL20 datasheet
 


Specifications of EE80C188XL20

Processor Type80C186FeaturesXL suffix, 16-Bit
Speed20MHzVoltage5V
Mounting TypeSurface MountPackage / Case68-PLCC
Family NameIntel186Device Core80188
Device Core Size16bFrequency (max)20MHz
Instruction Set ArchitectureCISCSupply Voltage 1 (typ)5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)4.5V
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count68
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names863554  
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80C186XL 80C188XL
Pin
Pin
Input
Output
Name
Type
Type
States
V
P
CC
V
G
SS
RESET
O
H(0)
R(1)
X1
I
A(E)
X2
O
H(Q)
R(Q)
CLKOUT
O
H(Q)
R(Q)
RES
I
A(L)
TEST BUSY
I
A(E)
(TEST)
NOTE
Pin names in parentheses apply to the 80C188XL
10
Table 3 Pin Descriptions
Pin Description
System Power
5 volt power supply
a
System Ground
RESET Output indicates that the CPU is being reset and can
be used as a system reset It is active HIGH synchronized
with the processor clock and lasts an integer number of
clock periods corresponding to the length of the RES signal
Reset goes inactive 2 clockout periods after RES goes
inactive When tied to the TEST BUSY pin RESET forces
the processor into enhanced mode RESET is not floated
during bus hold
Crystal Inputs X1 and X2 provide external connections for a
fundamental mode or third overtone parallel resonant crystal
for the internal oscillator X1 can connect to an external
clock instead of a crystal In this case minimize the
capacitance on X2 The input or oscillator frequency is
internally divided by two to generate the clock signal
(CLKOUT)
Clock Output provides the system with a 50% duty cycle
waveform All device pin timings are specified relative to
CLKOUT CLKOUT is active during reset and bus hold
An active RES causes the processor to immediately
terminate its present activity clear the internal logic and
enter a dormant state This signal may be asynchronous to
the clock The processor begins fetching instructions
approximately 6
clock cycles after RES is returned HIGH
For proper initialization V
must be within specifications
CC
and the clock signal must be stable for more than 4 clocks
with RES held LOW RES is internally synchronized This
input is provided with a Schmitt-trigger to facilitate power-on
RES generation via an RC network
The TEST pin is sampled during and after reset to determine
whether the processor is to enter Compatible or Enhanced
Mode Enhanced Mode requires TEST to be HIGH on the
rising edge of RES and LOW four CLKOUT cycles later Any
other combination will place the processor in Compatible
Mode During power-up active RES is required to configure
TEST BUSY as an input A weak internal pullup ensures a
HIGH state when the input is not externally driven
TEST In Compatible Mode this pin is configured to operate
as TEST This pin is examined by the WAIT instruction If the
TEST input is HIGH when WAIT execution begins instruction
execution will suspend TEST will be resampled every five
clocks until it goes LOW at which time execution will
resume If interrupts are enabled while the processor is
waiting for TEST interrupts will be serviced
BUSY (80C186XL Only) In Enhanced Mode this pin is
configured to operate as BUSY The BUSY input is used to
notify the 80C186XL of Math Coprocessor activity Floating
point instructions executing in the 80C186XL sample the
BUSY pin to determine when the Math Coprocessor is ready
to accept a new command BUSY is active HIGH