IC MPU 16BIT 5V 20MHZ 68PLCC

EE80C188XL20

Manufacturer Part NumberEE80C188XL20
DescriptionIC MPU 16BIT 5V 20MHZ 68PLCC
ManufacturerIntel
EE80C188XL20 datasheet
 


Specifications of EE80C188XL20

Processor Type80C186FeaturesXL suffix, 16-Bit
Speed20MHzVoltage5V
Mounting TypeSurface MountPackage / Case68-PLCC
Family NameIntel186Device Core80188
Device Core Size16bFrequency (max)20MHz
Instruction Set ArchitectureCISCSupply Voltage 1 (typ)5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)4.5V
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count68
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names863554  
1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Page 11/48

Download datasheet (401Kb)Embed
PrevNext
Table 3 Pin Descriptions (Continued)
Pin
Pin
Input
Name
Type
Type
TMR IN 0
I
A(L)
TMR IN 1
A(E)
TMR OUT 0
O
TMR OUT 1
DRQ0
I
A(L)
DRQ1
NMI
I
A(E)
INT0
I
A(E)
INT1 SELECT
A(L)
INT2 INTA0
I O
A(E)
INT3 INTA1 IRQ
A(L)
A19 S6
O
A18 S5
A17 S4
A16 S3
(A8– A15)
AD0 –AD15
I O
S(L)
(AD0–AD7)
NOTE
Pin names in parentheses apply to the 80C188XL
Output
Pin Description
States
Timer Inputs are used either as clock or control signals
depending upon the programmed timer mode These
inputs are active HIGH (or LOW-to-HIGH transitions are
counted) and internally synchronized Timer Inputs must
be tied HIGH when not being used as clock or retrigger
inputs
H(Q)
Timer outputs are used to provide single pulse or
continuous waveform generation depending upon the
R(1)
timer mode selected These outputs are not floated
during a bus hold
DMA Request is asserted HIGH by an external device
when it is ready for DMA Channel 0 or 1 to perform a
transfer These signals are level-triggered and internally
synchronized
The Non-Maskable Interrupt input causes a Type 2
interrupt An NMI transition from LOW to HIGH is
latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be
asserted for at least one CLKOUT period The Non-
Maskable Interrupt cannot be avoided by programming
Maskable Interrupt Requests can be requested by
activating one of these pins When configured as inputs
these pins are active HIGH Interrupt Requests are
H(1)
synchronized internally INT2 and INT3 may be
R(Z)
configured to provide active-LOW interrupt-
acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To
ensure recognition all interrupt requests must remain
active until the interrupt is acknowledged When Slave
Mode is selected the function of these pins changes
(see Interrupt Controller section of this data sheet)
H(Z)
Address Bus Outputs and Bus Cycle Status (3 – 6)
indicate the four most significant address bits during T
R(Z)
These signals are active HIGH
During T
T
T
and T
the S6 pin is LOW to indicate
2
3
W
4
a CPU-initiated bus cycle or HIGH to indicate a DMA-
initiated or refresh bus cycle During the same T-states
S3 S4 and S5 are always LOW On the 80C188XL
A15 – A8 provide valid address information for the entire
bus cycle
H(Z)
Address Data Bus signals constitute the time
multiplexed memory or I O address (T
R(Z)
T
T
and T
) bus The bus is active HIGH For the
3
W
4
80C186XL A
is analogous to BHE for the lower byte of
0
the data bus pins D
through D
7
when a byte is to be transferred onto the lower portion
of the bus in memory or I O operations
80C186XL 80C188XL
1
) and data (T
1
2
It is LOW during T
0
1
11