EE80C188XL20 Intel, EE80C188XL20 Datasheet - Page 11

IC MPU 16BIT 5V 20MHZ 68PLCC

EE80C188XL20

Manufacturer Part Number
EE80C188XL20
Description
IC MPU 16BIT 5V 20MHZ 68PLCC
Manufacturer
Intel
Datasheet

Specifications of EE80C188XL20

Processor Type
80C186
Features
XL suffix, 16-Bit
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Family Name
Intel186
Device Core
80188
Device Core Size
16b
Frequency (max)
20MHz
Instruction Set Architecture
CISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
863554

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NOTE
Pin names in parentheses apply to the 80C188XL
TMR IN 0
TMR IN 1
TMR OUT 0
TMR OUT 1
DRQ0
DRQ1
NMI
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
A19 S6
A18 S5
A17 S4
A16 S3
(A8– A15)
AD0 –AD15
(AD0–AD7)
Name
Pin
Type
Pin
I O
I O
O
O
I
I
I
I
Input
Type
A(L)
A(E)
A(L)
A(E)
A(E)
A(L)
A(E)
A(L)
S(L)
Table 3 Pin Descriptions (Continued)
Output
States
H(Q)
R(1)
H(1)
R(Z)
H(Z)
R(Z)
H(Z)
R(Z)
Timer Inputs are used either as clock or control signals
depending upon the programmed timer mode These
inputs are active HIGH (or LOW-to-HIGH transitions are
counted) and internally synchronized Timer Inputs must
be tied HIGH when not being used as clock or retrigger
inputs
Timer outputs are used to provide single pulse or
continuous waveform generation depending upon the
timer mode selected These outputs are not floated
during a bus hold
DMA Request is asserted HIGH by an external device
when it is ready for DMA Channel 0 or 1 to perform a
transfer These signals are level-triggered and internally
synchronized
The Non-Maskable Interrupt input causes a Type 2
interrupt An NMI transition from LOW to HIGH is
latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be
asserted for at least one CLKOUT period The Non-
Maskable Interrupt cannot be avoided by programming
Maskable Interrupt Requests can be requested by
activating one of these pins When configured as inputs
these pins are active HIGH Interrupt Requests are
synchronized internally INT2 and INT3 may be
configured to provide active-LOW interrupt-
acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To
ensure recognition all interrupt requests must remain
active until the interrupt is acknowledged When Slave
Mode is selected the function of these pins changes
(see Interrupt Controller section of this data sheet)
Address Bus Outputs and Bus Cycle Status (3 – 6)
indicate the four most significant address bits during T
These signals are active HIGH
During T
a CPU-initiated bus cycle or HIGH to indicate a DMA-
initiated or refresh bus cycle During the same T-states
S3 S4 and S5 are always LOW On the 80C188XL
A15 – A8 provide valid address information for the entire
bus cycle
Address Data Bus signals constitute the time
multiplexed memory or I O address (T
T
80C186XL A
the data bus pins D
when a byte is to be transferred onto the lower portion
of the bus in memory or I O operations
3
T
W
and T
2
T
3
4
0
) bus The bus is active HIGH For the
T
is analogous to BHE for the lower byte of
W
and T
Pin Description
7
through D
4
the S6 pin is LOW to indicate
0
80C186XL 80C188XL
It is LOW during T
1
) and data (T
1
2
1
11

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