IC MPU 16BIT 5V 20MHZ 68PLCC

EE80C188XL20

Manufacturer Part NumberEE80C188XL20
DescriptionIC MPU 16BIT 5V 20MHZ 68PLCC
ManufacturerIntel
EE80C188XL20 datasheet
 


Specifications of EE80C188XL20

Processor Type80C186FeaturesXL suffix, 16-Bit
Speed20MHzVoltage5V
Mounting TypeSurface MountPackage / Case68-PLCC
Family NameIntel186Device Core80188
Device Core Size16bFrequency (max)20MHz
Instruction Set ArchitectureCISCSupply Voltage 1 (typ)5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)4.5V
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count68
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names863554  
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80C186XL 80C188XL
Table 3 Pin Descriptions (Continued)
Pin
Pin
Input
Name
Type
Type
UCS
I O
A(L)
LCS
I O
A(L)
MCS0 PEREQ
I O
A(L)
MCS1 ERROR
MCS2
O
MCS3 NPS
PCS0
O
PCS1
PCS2
PCS3
PCS4
PCS5 A1
O
NOTE
Pin names in parentheses apply to the 80C188XL
14
Output
Pin Description
States
H(1)
Upper Memory Chip Select is an active LOW output
whenever a memory reference is made to the defined
R(WH)
upper portion (1K – 256K block) of memory The
address range activating UCS is software
programmable
UCS and LCS are sampled upon the rising edge of
RES If both pins are held low the processor will enter
ONCE Mode In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET UCS has a weak internal pullup that is active
during RESET to ensure that the processor does not
enter ONCE Mode inadvertently
H(1)
Lower Memory Chip Select is active LOW whenever a
memory reference is made to the defined lower portion
R(WH)
(1K – 256K) of memory The address range activating
LCS is software programmable
UCS and LCS are sampled upon the rising edge of
RES If both pins are held low the processor will enter
ONCE Mode In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET LCS has a weak internal pullup that is active
only during RESET to ensure that the processor does
not enter ONCE mode inadvertently
H(1)
Mid-Range Memory Chip Select signals are active LOW
when a memory reference is made to the defined mid-
R(WH)
range portion of memory (8K – 512K) The address
H(1)
ranges activating MCS0 – 3 are software programmable
R(1)
On the 80C186XL in Enhanced Mode MCS0 becomes
a PEREQ input (Processor Extension Request) When
connected to the Math Coprocessor this input is used
to signal the 80C186XL when to make numeric data
transfers to and from the coprocessor MCS3 becomes
NPS (Numeric Processor Select) which may only be
activated by communication to the 80C187 MCS1
becomes ERROR in Enhanced Mode and is used to
signal numerics coprocessor errors
H(1)
Peripheral Chip Select signals 0 – 4 are active LOW
when a reference is made to the defined peripheral
R(1)
area (64 Kbyte I O or 1 MByte memory space) The
address ranges activating PCS0 – 4 are software
programmable
H(1) H(X)
Peripheral Chip Select 5 or Latched A1 may be
programmed to provide a sixth peripheral chip select or
R(1)
to provide an internally latched A1 signal The address
range activating PCS5 is software-programmable
PCS5 A1 does not float during bus HOLD When
programmed to provide latched A1 this pin will retain
the previously latched value during HOLD