IC MPU 16BIT 5V 20MHZ 68PLCC

EE80C188XL20

Manufacturer Part NumberEE80C188XL20
DescriptionIC MPU 16BIT 5V 20MHZ 68PLCC
ManufacturerIntel
EE80C188XL20 datasheet
 


Specifications of EE80C188XL20

Processor Type80C186FeaturesXL suffix, 16-Bit
Speed20MHzVoltage5V
Mounting TypeSurface MountPackage / Case68-PLCC
Family NameIntel186Device Core80188
Device Core Size16bFrequency (max)20MHz
Instruction Set ArchitectureCISCSupply Voltage 1 (typ)5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)4.5V
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count68
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names863554  
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80C186XL 80C188XL
INSTRUCTION SET SUMMARY
Function
DATA TRANSFER
MOV
Move
e
Register to Register Memory
1 0 0 0 1 0 0 w
Register memory to register
1 0 0 0 1 0 1 w
Immediate to register memory
1 1 0 0 0 1 1 w
Immediate to register
1 0 1 1 w reg
Memory to accumulator
1 0 1 0 0 0 0 w
Accumulator to memory
1 0 1 0 0 0 1 w
Register memory to segment register
1 0 0 0 1 1 1 0
Segment register to register memory
1 0 0 0 1 1 0 0
PUSH
Push
e
Memory
1 1 1 1 1 1 1 1
Register
0 1 0 1 0 reg
Segment register
0 0 0 reg 1 1 0
Immediate
0 1 1 0 1 0 s 0
PUSHA
Push All
0 1 1 0 0 0 0 0
e
POP
Pop
e
Memory
1 0 0 0 1 1 1 1
Register
0 1 0 1 1 reg
Segment register
0 0 0 reg 1 1 1
POPA
Pop All
0 1 1 0 0 0 0 1
e
XCHG
Exchange
e
Register memory with register
1 0 0 0 0 1 1 w
Register with accumulator
1 0 0 1 0 reg
IN
Input from
e
Fixed port
1 1 1 0 0 1 0 w
Variable port
1 1 1 0 1 1 0 w
OUT
Output to
e
Fixed port
1 1 1 0 0 1 1 w
Variable port
1 1 1 0 1 1 1 w
XLAT
Translate byte to AL
1 1 0 1 0 1 1 1
e
Load EA to register
1 0 0 0 1 1 0 1
LEA
e
Load pointer to DS
1 1 0 0 0 1 0 1
LDS
e
LES
Load pointer to ES
1 1 0 0 0 1 0 0
e
LAHF
Load AH with flags
1 0 0 1 1 1 1 1
e
SAHF
Store AH into flags
1 0 0 1 1 1 1 0
e
PUSHF
Push flags
1 0 0 1 1 1 0 0
e
POPF
Pop flags
1 0 0 1 1 1 0 1
e
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers
42
Format
mod reg r m
mod reg r m
mod 000 r m
data
data if w
1
e
data
data if w
1
e
addr-low
addr-high
addr-low
addr-high
mod 0 reg r m
mod 0 reg r m
mod 1 1 0 r m
data
data if s
0
e
mod 0 0 0 r m
(reg
01)
i
mod reg r m
port
port
mod reg r m
mod reg r m
(mod
11)
i
mod reg r m
(mod
11)
i
80C186XL
80C188XL
Clock
Clock
Comments
Cycles
Cycles
2 12
2 12
2 9
2 9
12 13
12 13
8 16-bit
3 4
3 4
8 16-bit
8
8
9
9
2 9
2 13
2 11
2 15
16
20
10
14
9
13
10
14
36
68
20
24
10
14
8
12
51
83
4 17
4 17
3
3
10
10
8
8
9
9
7
7
11
15
6
6
18
26
18
26
2
2
3
3
9
13
8
12