IC MPU 16BIT 5V 20MHZ 68PLCC

EE80C188XL20

Manufacturer Part NumberEE80C188XL20
DescriptionIC MPU 16BIT 5V 20MHZ 68PLCC
ManufacturerIntel
EE80C188XL20 datasheet
 


Specifications of EE80C188XL20

Processor Type80C186FeaturesXL suffix, 16-Bit
Speed20MHzVoltage5V
Mounting TypeSurface MountPackage / Case68-PLCC
Family NameIntel186Device Core80188
Device Core Size16bFrequency (max)20MHz
Instruction Set ArchitectureCISCSupply Voltage 1 (typ)5V
Operating Supply Voltage (max)5.5VOperating Supply Voltage (min)4.5V
Operating Temp Range0C to 70COperating Temperature ClassificationCommercial
MountingSurface MountPin Count68
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names863554  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
Page 47/48

Download datasheet (401Kb)Embed
PrevNext
INSTRUCTION SET SUMMARY
Function
PROCESSOR CONTROL
Clear carry
1 1 1 1 1 0 0 0
CLC
e
Complement carry
1 1 1 1 0 1 0 1
CMC
e
STC
Set carry
1 1 1 1 1 0 0 1
e
CLD
Clear direction
1 1 1 1 1 1 0 0
e
STD
Set direction
1 1 1 1 1 1 0 1
e
CLI
Clear interrupt
1 1 1 1 1 0 1 0
e
STI
Set interrupt
1 1 1 1 1 0 1 1
e
HLT
Halt
1 1 1 1 0 1 0 0
e
WAIT
Wait
1 0 0 1 1 0 1 1
e
LOCK
Bus lock prefix
1 1 1 1 0 0 0 0
e
NOP
No Operation
1 0 0 1 0 0 0 0
e
(TTT LLL are opcode to processor extension)
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers
The Effective Address (EA) of the memory operand
is computed according to the mod and r m fields
if mod
11 then r m is treated as a REG field
e
if mod
00 then DISP
0 disp-low and disp-
e
e
high are absent
if mod
01 then DISP
disp-low sign-ex-
e
e
tended to 16-bits disp-high is absent
if mod
10 then DISP
disp-high disp-low
e
e
if r m
000 then EA
(BX)
(SI)
e
e
a
if r m
001 then EA
(BX)
(DI)
e
e
a
if r m
010 then EA
(BP)
(SI)
e
e
a
if r m
011 then EA
(BP)
(DI)
e
e
a
if r m
100 then EA
(SI)
DISP
e
e
a
if r m
101 then EA
(DI)
DISP
e
e
a
if r m
110 then EA
(BP)
DISP
e
e
a
if r m
111 then EA
(BX)
DISP
e
e
a
DISP follows 2nd byte of instruction (before data if
required)
except if mod
00 and r m
110 then EA
e
e
disp-high disp-low
EA calculation time is 4 clock cycles for all modes
and is included in the execution times given whenev-
er appropriate
Segment Override Prefix
0 0 1 reg 1 1 0
(Continued)
Format
reg is assigned according to the following
reg
00
01
10
11
DISP
a
DISP
a
REG is assigned according to the following table
DISP
a
DISP
16-Bit (w
a
e
000 AX
001 CX
010 DX
011 BX
100 SP
101 BP
110 SI
e
111 DI
The physical addresses of all operands addressed
by the BP register are computed using the SS seg-
ment register The physical addresses of the desti-
nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment which may not be overridden
80C186XL 80C188XL
80C186XL
80C188XL
Clock
Clock
Comments
Cycles
Cycles
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
6
6
if TEST
0
e
2
2
3
3
Segment
Register
ES
CS
SS
DS
1)
8-Bit (w
0)
e
000 AL
001 CL
010 DL
011 BL
100 AH
101 CH
110 DH
111 BH
47