LUPXA255A0C400 Intel, LUPXA255A0C400 Datasheet - Page 15

• Manufacturer Part Number: LUPXA255A0C400
• Description: IC MICRO PROCESSOR 400MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C400

• Processor Type: XScale®
• Speed: 400MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 867748

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
AC97 Controller and I
BITCLK/
GPIO[28]
SDATA_IN0/
GPIO[29]
SDATA_IN1/
GPIO[32]
SDATA_OUT/
GPIO[30]
SYNC/
GPIO[31]
nACRESET
I
SCL
SDA
PWM Pins
PWM[1:0]/
GPIO[17:16]
DMA Pins
DREQ[1:0]/
GPIO[19:20]
GPIO Pins
GPIO[1:0]
GPIO[14:2]
GPIO[22:21]
Crystal and Clock Pins
PXTAL
PEXTAL
TXTAL
2
C Controller Pins
Pin Name
Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
OC
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
OA
IA
OA
Type
2
S Controller Pins
AC97 audio port bit clock. (input) AC97 clock is
generated by Codec 0 and fed into the PXA255
processor processor and Codec 1.
AC97 Aaudio port bit clock. (output) AC97 clock is
generated by the PXA255 processor.
I
and fed into PXA255 processor.
I
PXA255 processor.
AC97 audio port data in. (input) Input line for Codec 0.
I
AC97 audio port data in. (input) Input line for Codec 1.
I
controller.
AC97 audio port data out. (output) Output from the
PXA255 processor to Codecs 0 and 1.
I
AC97 audio port sync signal. (output) Frame sync
signal for the AC97 controller.
I
controller.
AC97 audio port reset signal. (output)
I
I
Pulse width modulation channels 0 and 1. (outputs)
DMA request. (input) Notifies the DMA Controller that an
external device requires a DMA transaction. DREQ[1] is
GPIO[19]. DREQ[0] is GPIO[20].
General purpose I/O. Wakeup sources on both rising
and falling edges on nRESET.
General purpose I/O. More wakeup sources for sleep
mode.
General purpose I/O. Additional General Purpose I/O
pins.
3.6864 MHz crystal input. No external caps are
required.
3.6864 MHz crystal output. No external caps are
required.
32 KHz crystal input. No external caps are required.
2
2
2
2
2
2
2
2
S bit clock. (input) I
S bit clock. (output) I
S data in. (input) Input line for the I
S system clock. (output) System clock from I
S data out. (output) Output line for the I
S sync. (output) Frame sync signal for the I
C clock. (bidirectional)
C data. (bidirectional).
Signal Descriptions
2
S clock is generated externally
2
S clock is generated by the
2
S controller.
2
S controller.
2
S
2
S
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Driven Low
Hi-Z
Hi-Z
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Note [2]
Note [2]
Note [2]
Reset State
Package Information
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Driven Low
Hi-Z
Hi-Z
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [2]
Note [2]
Note [2]
Sleep State
15