LUPXA255A0C400 Intel, LUPXA255A0C400 Datasheet - Page 16

• Manufacturer Part Number: LUPXA255A0C400
• Description: IC MICRO PROCESSOR 400MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C400

• Processor Type: XScale®
• Speed: 400MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 867748

Package Information
16
TEXTAL
L_DD[12]/
GPIO[70]
L_DD[13]/
GPIO[71]
L_DD[14]/
GPIO[72]
48MHz/GP[7]
RTCCLK/
GP[10]
3.6MHz/GP[11]
32kHz/GP[12]
Miscellaneous Pins
BOOT_SEL
[2:0]
PWR_EN
nBATT_FAULT
nVDD_FAULT
nRESET
Pin Name
Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)
IA
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
IC
OC
IC
IC
IC
Type
32 kHz crystal output. No external caps are required.
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
RTC clock. (output) Real time clock 1 Hz tick.
LCD display data. (output) Transfers the pixel
information from the LCD controller to the external LCD
panel.
3.6864 MHz clock. (output) Output from 3.6864 MHz
oscillator.
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
32 kHz clock. (output) Output from the 32 kHz oscillator.
48 MHz clock. (output) Peripheral clock output derived
from the PLL.
NOTE: This clock is only generated when the USB unit
Real time clock. (output) 1 Hz output derived from the
32 kHz or 3.6864 MHz output.
3.6864 MHz clock. (output) Output from 3.6864 MHz
oscillator.
32 kHz clock. (output) Output from the 32 kHz oscillator.
Boot select pins. (input) Indicates type of boot device.
Power Enable for the power supply. (output) When
negated, it signals the power supply to remove power to
the core because the system is entering sleep mode.
Main Battery Fault. (input) Signals that main battery is
low or removed. Assertion causes PXA255 processor
processor to enter sleep mode or force an imprecise data
exception, which cannot be masked. PXA255 processor
will not recognize a wake-up event while this signal is
asserted. Minimum assertion time for nBATT_FAULT is 1
ms.
VDD Fault. (input) Signals that the main power source is
going out of regulation. nVDD_FAULT causes the
PXA255 processor to enter sleep mode or force an
imprecise data exception, which cannot be masked.
nVDD_FAULT is ignored after a wake-up event until the
power supply timer completes (approximately 10 ms).
Minimum assertion time for nVDD_FAULT is 1 ms.
Hard reset. (input) Level -sensitive input used to start the
processor from a known address. Assertion terminates
the current instruction abnormally and causes a reset.
When nRESET is driven high, the processor starts
execution from address 0. nRESET must remain low until
the power supply is stable and the internal 3.6864 MHz
oscillator has stabilized.
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
clock enable is set.
Signal Descriptions
Note [2]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Input
Driven High
Input
Input
Input
Reset State
Note [2]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Input
Driven low while
entering sleep
mode. Driven high
when sleep exit
sequence begins.
Input
Input
Input. Driving low
during sleep will
cause normal
reset sequence
and exit from sleep
mode.
Sleep State