LUPXA255A0C400 Intel, LUPXA255A0C400 Datasheet - Page 9

• Manufacturer Part Number: LUPXA255A0C400
• Description: IC MICRO PROCESSOR 400MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C400

• Processor Type: XScale®
• Speed: 400MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 867748

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Memory Controller Pins
MA[25:0]
MD[15:0]
MD[31:16]
nOE
nWE
nSDCS[3:0]
DQM[3:0]
nSDRAS
nSDCAS
SDCKE[0]
Pin Name
Table 2.
Table 3.
Some of the processor pins can be connected to multiple signals. The GAFRn_m registers
determine the signal connected to the pin. Some signals can go to multiple pins. The signal must be
routed to one pin only by using the GAFRn_m registers. Because this is true, some pins are listed
twice—once in each unit that can use the pin. Not all peripherals can be used simutaneously in one
design because different peripherals share the same pins.
Processor Pin Types
Pin and Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
OCZ
ICOCZ
ICOCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OCZ
OC
IC
OC
OCZ
ICOCZ
IA
OA
IAOA
SUP
Type
Type
Memory address bus. (output) Signals the address
requested for memory accesses.
Memory data bus. (input/output) Lower 16 bits of the
data bus.
Memory data bus. (input/output) Used for 32-bit
memories.
Memory output enable. (output) Connect to the output
enables of memory devices to control data bus drivers.
Memory write enable. (output) Connect to the write
enables of memory devices.
SDRAM CS for banks 3 through 0. (output) Connect to
the chip select (CS) pins for SDRAM. For the PXA255
processor processor nSDCS0 can be Hi-Z, nSDCS1-3
cannot.
SDRAM DQM for data bytes 3 through 0. (output)
Connect to the data output mask enables (DQM) for
SDRAM.
SDRAM RAS. (output) Connect to the row address
strobe (RAS) pins for all banks of SDRAM.
SDRAM CAS. (output) Connect to the column address
strobe (CAS) pins for all banks of SDRAM.
Synchronous Static Memory clock enable. (output)
Connect to the CKE pins of SMROM. The memory
controller provides control register bits for de-assertion.
CMOS input
CMOS output
CMOS output, Hi-Z
CMOS bidirectional, Hi-Z
Analog Input
Analog output
Analog bidirectional
Supply pin (either VCC or VSS)
Signal Descriptions
Function
Driven Low
Hi-Z
Hi-Z
Driven High
Driven High
Driven High
Driven Low
Driven High
Driven High
Driven Low
Reset State
Package Information
Driven Low
Driven Low
Driven Low
Note [4]
Note [4]
Note [5]
Driven Low
Driven High
Driven High
Driven Low
Sleep State
9