PRIXP425BD Intel, PRIXP425BD Datasheet - Page 94

• Manufacturer Part Number: PRIXP425BD
• Description: IC NETWRK PROCESSR 533MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BD

• Processor Type: Network
• Features: XScale Core
• Speed: 533MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 866108

Intel
Electrical Specifications
Table 52.
Figure 26.
94
®
IXP42X Product Line and IXC1100 Control Plane Processor
Intel Multiplexed Mode Values
NOTES:
Intel Simplex Mode
Talepulse
Tale2addrhold
Tdval2valwrt
Twrpulse
Tdholdafterwr
Tale2valcs
Trdsetup
Trdhold
Trecov
1. The EX_ALE signal is extended form 1 to 4 cycles based on the programming of the T1 timing parameter.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
7. One cycle is the period of the Expansion Bus clock.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
9. Timing tests were performed with a 70-pF capacitor to ground.
The parameter Tale2addrhold is fixed at 1 cycle.
strobe (read or write) to an external device.
write) to an external device. Data will be available during this time as well.
data (during a write) will be held.
expansion interface.
synchronous mode.
Symbol
EX_ADDR
EX_CS_N
EX_WR_N
EX_RD_N
EX_DATA
EX_DATA
EX_CLK
Pulse width of ALE (ADDR is valid at the rising edge of ALE)
Valid address hold time after from falling edge of ALE
Write data valid prior to WR_N falling edge
Pulse width of the WR_N
Valid data after the rising edge of WR_N
Valid chip select after the falling edge of ALE
Data valid required before the rising edge of RD_N
Data hold required after the rising edge of RD_N
Time needed between successive accesses on expansion
interface.
T addr2valcs
1-4 Cycles
T1
Parameter
T dval2valwrt
1-4 Cycles
T2
Valid Address
1-16 Cycles
Output Data
T wrpulse
T rdsetup
T3
Input Data
T dhold2afterwr
1-4 Cycles
T4
T rdhold
Min.
5.3
1
1
1
1
1
1
2
1
1-16 Cycles
T recov
T5
Max.
14.7
41
16
16
1
4
4
4
Cycles 1,
Cycles 1, 2,
Cycles 3,
Cycles 4,
Cycles 5,
Cycles
Cycles
Units
ns
ns
A9586-01
Datasheet
7
6
Notes
7
7
7
7
7