EE80960SA16512 Intel, EE80960SA16512 Datasheet
EE80960SA16512
Specifications of EE80960SA16512
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EE80960SA16512 Summary of contents
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... Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ trademark of Digital Equipment Corporation) Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. ...
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EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS CONTENTS ® 1.0 THE i960 PROCESSOR ...........................................................................................................................1 1.1 Key Performance Features .................................................................................................................2 1.1.1 Memory Space And Addressing Modes ................................................................................... 4 1.1.2 Data Types ...............................................................................................................................4 1.1.3 Large Register Set ...................................................................................................................4 1.1.4 Multiple Register ...
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LIST OF FIGURES Figure 1 The 80960SA Processor’s Highly Parallel Architecture ................................................................ 0 Figure 2 80960SA Programming Environment ........................................................................................... 1 Figure 3 Instruction Formats ...................................................................................................................... 4 Figure 4 Multiple Register Sets Are Stored On-Chip .................................................................................. 5 Figure 5 Connection Recommendation ...
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... THE i960 PROCESSOR The 80960SA is a member of the 32-bit architecture from Intel known as the i960 processor family. These microprocessors were especially designed to serve the needs of embedded applications. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and networking ...
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... Key Performance Features The 80960SA architecture is based on the most recent advances in microprocessor technology and is grounded in Intel’s long experience in the design and manufacture of embedded microprocessors. Many features contribute to the 80960SA’s excep- tional performance: 1. Large Register Set. Having a large number of registers reduces the number of times that a processor needs to access memory ...
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Table 1. 80960SA Instruction Set Data Movement Arithmetic Load Add Store Subtract Move Multiply Load Address Divide Remainder Modulo Shift Extended Multiply Extended Divide Comparison Branch Compare Unconditional Branch Conditional Compare Conditional Branch Compare and Increment Compare and Branch Compare ...
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Control Opcode Compare and Opcode Branch Register to Opcode Register Memory Access--- Opcode Short Memory Access--- Opcode Long 1.1.1 Memory Space And Addressing Modes The 80960SA offers a linear environment so that all programs running on the processor are ...
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The term global refers to the fact that these registers retain their contents procedure calls. The local registers, on the other hand, are procedure specific. For each procedure call, the 80960SA allocates ...
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Instruction Cache To further reduce memory accesses, the 80960SA includes a 512-byte on-chip instruction cache. The instruction cache is based on the concept of locality of reference; most programs are not usually executed in a steady stream but ...
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... CHMOS The 80960SA is fabricated using Intel’s CHMOS IV (Complementary High Speed Metal Oxide Semicon- ductor) process. The 80960SA is available at 10 and 16 MHz in the QFP package and at 10, 16 and 20 MHz in the PLCC package ...
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Table 3. 80960SA Pin Description: Bus Signals (Sheet NAME TYPE CLK2 I SYSTEM CLOCK provides the fundamental timing for 80960SA systems divided by two inside the 80960SA to generate the internal processor clock. A31:16 ...
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Table 3. 80960SA Pin Description: Bus Signals (Sheet NAME TYPE LOCK I/O BUS LOCK prevents bus masters from gaining control of the bus during O.D. Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert LOCK. ...
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Table 4. 80960SA Pin Description: Support Signals NAME TYPE RESET I RESET clears the processor’s internal logic and causes it to reinitialize. During RESET assertion, the input pins are ignored (except for INT0, INT1, INT3, LOCK), the three-state output ...
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ELECTRICAL SPECIFICATIONS 2.1 Power and Grounding The 80960SA is implemented in CHMOS IV technology and therefore has modest power require- ments. Its high clock frequency and numerous output buffers (address/data, control, error and arbitration signals) can cause power surges ...
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V = 5.0V CC 300 250 20 MHz 16 MHz 10 MHz 200 150 100 -10 Figure 6. Typical Supply Current vs. Case Temperature TEMP = +22°C 4.5V 5.0V 5.5V Figure 7. Typical Current vs. Frequency (Room Temp) ...
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TEMP = +85°C 300 4.5V 5.0V 250 5.5V 200 150 100 OPERATING FREQUENCY (MHz) Figure 8. Typical Current vs. Frequency (Hot Temp) 2.5 Test Load Circuit Figure 10 illustrates the load circuit used to test ...
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ABSOLUTE MAXIMUM RATINGS* Parameter Maximum Rating O perating Temperature (PLCC) ........... 0°C to +85°C Case Operating Temperature (QFP) ............ 0°C to +100°C Case Storage Temperature .............................. –65°C to +150°C Voltage on Any Pin (PLCC)................. –0.5V to VCC +0.5V ...
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AC Specifications This section describes the AC specifications for the 80960SA pins. All input and output timings are specified relative to the 1.5V level of the rising edge of CLK2 and refer to the time at which the signal ...
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Table 6. 80960SA AC Characteristics (10 MHz) Symbol Parameter Input Clock T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time 3 (CLK2) T Processor Clock Fall Time (CLK2 ...
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Table 7. 80960SA AC Characteristics (16 MHz) Symbol Parameter Input Clock T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time 3 (CLK2) T Processor Clock Fall Time (CLK2 Processor ...
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Table 8. 80960SA AC Characteristics (20 MHz) Symbol Parameter Input Clock T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time (CLK2 Processor Clock Fall Time (CLK2 ...
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HIGH LEVEL (MIN) 0.7V CC LOW LEVEL (MAX) 0. Figure 12. Processor Clock Pulse (CLK2) CLK2 CLK OUTPUTS RESET INT0, INT1, INT3, LOCK NOTE: Initialization parameters must be set up at least four CLK2 periods before the first ...
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T h CLK2 CLK T 12 HOLD T 6 HLDA Figure 14. HOLD Timing 6 ...
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... Packaging The 80960SA is available in two package types: • 80-lead quad flat pack (EIAJ QFP). Shown in Figure 15. • 84-lead plastic leaded chip carrier (PLCC). Shown in Figure 16. Dimensions for both package types are given in the Intel Packaging handbook (Order #240800 ALE 67 READY 68 ...
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A20 12 13 A19 14 A18 15 A17 A16 AD15 AD14 AD13 24 25 AD12 AD11 ...
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Pinout Table 9. 80960SA QFP Pinout — In Pin Order Pin Signal Pin 1 A22 21 2 A21 22 3 A20 23 4 A19 24 5 A18 25 6 A17 26 7 A16 ...
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Table 10. 80960SA QFP Pinout — In Signal Order Signal Pin Signal A1 38 A18 A2 35 A19 A3 34 A20 AD1 30 A21 AD2 29 A22 AD3 28 A23 AD4 27 A24 AD5 26 A25 AD6 25 A26 ...
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Table 11. 80960SA PLCC Pinout — In Pin Order Pin Signal Pin A27 24 4 A26 25 5 A25 A24 29 9 ...
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Table 12. 80960SA PLCC Pinout — In Signal Order Signal Pin Signal A1 49 A18 A2 46 A19 A3 45 A20 D0 41 A21 AD1 40 A22 AD2 39 A23 AD3 38 A24 AD4 37 A25 AD5 36 A26 ...
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Package Thermal Specifications The 80960SA is specified for operation when case temperature is within the range 0°C to +85°C (PLCC) or 0°C to 100°C (QFP). Measure case temperature at the top center of the package. Ambient temper- ature can ...
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WAVEFORMS Figures 17, 18, 19, 20 and 21 show waveforms for various transactions on the 80960SA’s bus. Figure 22 shows a cold reset functional waveform CLK2 CLK ALE AS A31:16 A15:4, ADDR D15:0 A3:1 BE1:0 BLAST ...
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CLK2 CLK ALE AS A31:16 A15:4, ADDR D15:0 A3:1 000 BE1:0 BLAST W/R DT/R DEN READY Figure 18. Quad Word Burst Read Transaction With Wait States ...
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CLK2 CLK ALE AS A31:16 A15:4, ADDR DATA D15:0 A3:1 VALID BE1:0 0x BLAST W/R DT/R DEN READY Figure 19. Burst Write Transaction With Wait States (6-8 Bytes Transferred) ...
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Figure 20. Accesses Generated by Quad Word Read Bus Request, Misaligned One Byte from Quad Word Boundary Wait States 80960SA 31 ...
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CLK2 CLK ALE AS A31:16 A15:4, ADD D15:0 A3:1 BE1 INTA BLAST W/R DT/R DEN LOCK READY Figure 21. Interrupt Acknowledge Cycle ...
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CLK2 CLK V CC AS, DT/R, DEN, LOCK (O) HLDA BLAST/FAIL ALE, A31:16, A15:4, A3:1, D15:0, BE1:0, W/R RESET INT0, INT1, INT3, LOCK (I) V and CLK2 stable to RESET high, minimum 41 CLK2 periods ...
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REVISION HISTORY This data sheet supersedes data sheet 272206-001 and applies only to those devices identified as the current stepping in section 3.5. The sections significantly changed since the previous revision are: Section Overall 2.3 Connection Recommendations (pg. ...
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Section Table 6. 80960SA AC Characteristics (10 MHz) (pg. 17) Table 7. 80960SA AC Characteristics (16 MHz) (pg. 18). Table 8. 80960SA AC Characteristics (20 MHz) (pg. 19) Table 11. 80960SA PLCC Pinout — In Pin Order (pg. 26) Table ...