EE80C186EB25 Intel, EE80C186EB25 Datasheet - Page 11

• Manufacturer Part Number: EE80C186EB25
• Description: IC MPU 16-BIT 5V 25MHZ 84-PLCC
• Manufacturer: Intel

Specifications of EE80C186EB25

• Processor Type: 80C186
• Features: EB suffix, 16-Bit, Extended Temp
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 864179

NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
A18 16
A19 ONCE
(A15 A8)
(A18 16)
(A19 ONCE)
S2 0
ALE
BHE
(RFSH)
RD
WR
READY
DEN
Name
Pin
Type
Pin
I O
O
O
O
O
O
O
I
Input
Type
A(L)
A(L)
S(L)
Output
States
R(WH)
H(Z)
P(X)
H(Z)
R(Z)
H(0)
R(0)
H(Z)
R(Z)
P(X)
H(Z)
R(Z)
H(Z)
R(Z)
H(Z)
R(Z)
P(1)
P(0)
P(1)
P(1)
P(1)
Table 3 Pin Descriptions (Continued)
These pins provide multiplexed Address during the address
phase of the bus cycle Address bits 16 through 19 are presented
on these pins and can be latched using ALE These pins are
driven to a logic 0 during the data phase of the bus cycle On the
80C188EB A15 – A8 provide valid address information for the
entire bus cycle During a processor reset (RESIN active) A19
ONCE is used to enable ONCE mode A18 16 must not be driven
low during reset or improper operation may result
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
Address Latch Enable output is used to strobe address
information into a transparent type latch during the address phase
of the bus cycle
Byte High Enable output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus BHE and
A0 have the following logical encoding
A0
On the 80C188EB 80L188EB RFSH is asserted low to indicate a
refresh bus cycle
ReaD output signals that the accessed memory or I O device
must drive data information onto the data bus
WRite output signals that data available on the data bus are to be
written into the accessed memory or I O device
READY input to signal the completion of a bus cycle READY
must be active to terminate any bus cycle unless it is ignored by
correctly programming the Chip-Select Unit
Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when data is
to be transferred on the bus
S2
0
0
0
0
1
1
1
1
0
0
1
1
S1
0
0
1
1
0
0
1
1
BHE
0
1
0
1
S0
0
1
0
1
0
1
0
1
80C186EB 80C188EB 80L186EB 80L188EB
Interrupt Acknowledge
Read I O
Write I O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
Passive (no bus activity)
Encoding (for the 80C186EB 80L186EB only)
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
Description
Bus Cycle Initiated
11