EE80C186EB25 Intel, EE80C186EB25 Datasheet - Page 12

• Manufacturer Part Number: EE80C186EB25
• Description: IC MPU 16-BIT 5V 25MHZ 84-PLCC
• Manufacturer: Intel

Specifications of EE80C186EB25

• Processor Type: 80C186
• Features: EB suffix, 16-Bit, Extended Temp
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 864179

80C186EB 80C188EB 80L186EB 80L188EB
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
12
DT R
LOCK
HOLD
HLDA
NCS
(N C )
ERROR
(N C )
PEREQ
(N C )
UCS
LCS
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
Name
Pin
Type
Pin
O
O
O
O
O
O
O
I
I
I
Input
Type
A(L)
A(L)
A(L)
H(X) H(1)
P(X) P(1)
Table 3 Pin Descriptions (Continued)
Output
States
R(WH)
H(Z)
R(Z)
H(Z)
P(X)
P(1)
H(1)
R(0)
P(0)
H(1)
R(1)
P(1)
H(1)
R(1)
P(1)
H(1)
R(1)
P(1)
R(1)
Data Transmit Receive output controls the direction of a
bi-directional buffer in a buffered system DT R is only
available for the PLCC package
LOCK output indicates that the bus cycle in progress is not
to be interrupted The processor will not service other bus
requests (such as HOLD) while LOCK is active This pin is
configured as a weakly held high input while RESIN is
active and must not be driven low
HOLD request input to signal that an external bus master
wishes to gain control of the local bus The processor will
relinquish control of the local bus between instruction
boundaries not conditioned by a LOCK prefix
HoLD Acknowledge output to indicate that the processor
has relinquished control of the local bus When HLDA is
asserted the processor will (or has) floated its data bus
and control signals allowing another bus master to drive the
signals directly
Numerics Coprocessor Select output is generated when
accessing a numerics coprocessor NCS is not provided on
the QFP or SQFP packages This signal does not exist on
the 80C188EB 80L188EB
ERROR input that indicates the last numerics coprocessor
operation resulted in an exception condition An interrupt
TYPE 16 is generated if ERROR is sampled active at the
beginning of a numerics operation ERROR is not provided
on the QFP or SQFP packages This signal does not exist
on the 80C188EB 80L188EB
CoProcessor REQuest signals that a data transfer
between an External Numerics Coprocessor and Memory is
pending PEREQ is not provided on the QFP or SQFP
packages This signal does not exist on the 80C188EB
80L188EB
Upper Chip Select will go active whenever the address of
a memory or I O bus cycle is within the address limitations
programmed by the user After reset UCS is configured to
be active for memory accesses between 0FFC00H and
0FFFFFH
Lower Chip Select will go active whenever the address of
a memory bus cycle is within the address limitations
programmed by the user LCS is inactive after a reset
These pins provide a multiplexed function If enabled each
pin can provide a Generic Chip Select output which will go
active whenever the address of a memory or I O bus cycle
is within the address limitations programmed by the user
When not programmed as a Chip-Select each pin may be
used as a general purpose output Port As an output port
pin the value of the pin can be read internally
Description