EE80C188XL25 Intel, EE80C188XL25 Datasheet - Page 7

• Manufacturer Part Number: EE80C188XL25
• Description: IC MPU 16-BIT 5V 25MHZ 68-PLCC
• Manufacturer: Intel

Specifications of EE80C188XL25

• Processor Type: 80C188
• Features: XL suffix, 16-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863653

DRAM Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates DRAM refresh bus cycles The RCU operates
only in Enhanced Mode After a programmable peri-
od of time the RCU generates a memory read re-
quest to the BIU If the address generated during a
refresh bus cycle is within the range of a properly
programmed chip select that chip select will be acti-
vated when the BIU executes the refresh bus cycle
Power-Save Control
The 80C186XL when in Enhanced Mode can enter
a power saving state by internally dividing the proc-
essor clock frequency by a programmable factor
This divided frequency is also available at the
CLKOUT pin
All internal logic including the Refresh Control Unit
and the timers have their clocks slowed down by
the division factor To maintain a real time count or a
fixed DRAM refresh rate these peripherals must be
re-programmed when entering and leaving the pow-
er-save mode
Interface for 80C187 Math
Coprocessor (80C186XL Only)
In Enhanced Mode three of the mid-range memory
chip selects are redefined according to Table 1 for
use with the 80C187 The fourth chip select MCS2
functions as in compatible mode and may be pro-
grammed for activity with ready logic and wait states
accordingly As in Compatible Mode MCS2 will func-
tion for one-fourth a programmed block size
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system the 80C186XL has a test
mode available which allows all pins to be placed in
a high-impedance state ONCE stands for ‘‘ON Cir-
cuit Emulation’’ When placed in this mode the
80C186XL will put all pins in the high-impedance
state until RESET
The ONCE mode is selected by tying the UCS and
the LCS LOW during RESET These pins are sam-
pled on the low-to-high transition of the RES pin
The UCS and the LCS pins have weak internal pull-
up resistors similar to the RD and TEST BUSY pins
to guarantee ONCE Mode is not entered inadver-
tently during normal operation LCS and UCS must
be held low at least one clock after RES goes high
to guarantee entrance into ONCE Mode
Compatible
MCS0
MCS1
MCS2
MCS3
Mode
Table 1 MCS Assignments
PEREQ Processor Extension Request
ERROR NPX Error
MCS2
NPS
Mid-Range Chip Select
Numeric Processor Select
Enhanced Mode
80C186XL 80C188XL
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