LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 36

• Manufacturer Part Number: LUPXA255A0C200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866868

Electrical Specifications
36
Table 21. Card Interface (PCMCIA or Compact Flash) AC Specifications
Table 22. Synchronous Memory Interface AC Specifications
NOTE: These numbers are minimums. They can be much longer based on the programmable card
SDRAM / SMROM / SDRAM-Timing Synchronous Flash (Synchronous)
Fast Flash (Synchronous READS only)
NOTES:
tsynSDOH
tsynSDOS
1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.
2. SDCLK for SDRAM, SMROM, and SDRAM-timing Synchronous Flash can be at the slowest, divide-by-2 of
3. This number represents 1/2 SDCLK period.
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of
tsynSDIS
tsynCMD
tsynRCD
tcardCMD
tsynCLK
tsynCAS
Symbol
tsynDIH
tcardDH
Symbol
tcardAS
tcardAH
tcardDS
tffCEH
tffCLK
tffCES
tffADV
tffOS
the 99.5 MHz MEMCLK. It can be 99.5 MHz at the fastest.
the 132.7 MHz MEMCLK at its fastest.
tffAS
interface timing registers.
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
SDCLK period
nSDCAS, nSDRAS, nWE, nSDCS assert time
nSDRAS to nSDCAS assert time
nSDCAS to nSDCAS assert time
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,
nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0)
rise
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,
nWE, nOE, SDCKE(1:0), RDnWR output hold time from
SDCLK(2:0) rise
MD(31:0) read data input setup time from SDCLK(2:0) rise
MD(31:0) read data input hold time from SDCLK(2:0) rise
SDCLK period
MA(25:0) setup to nSDCAS (as nADV) asserted
nCS setup to nSDCAS (as nADV) asserted
nSDCAS (as nADV) pulse width
nSDCAS (as nADV) de-assertion to nOE assertion
nOE deassertion to nCS de-assertion
MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or
nPIOR asserted
MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or
nPIOR de-asserted
MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted
MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR de-asserted
nPWE, nPOE, nPIOW, or nPIOR command assertion
Description
Description
1
MIN
3.8
3.6
0.5
1.5
0.5
0.5
10
15
1
1
2
1
3
4
MAX
MEMCLKs
20
20
2
2
2
2
2
Units,
Notes
sdclk
sdclk
sdclk
sdclk
sdclk
sdclk
sdclk
sdclk
ns, 2
ns, 3
ns, 3
ns, 4
ns
ns