LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 17

• Manufacturer Part Number: LUPXA255A0C200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866868

16.
Problem:
Implication:
Workaround:
Status:
17.
Problem:
Implication:
Workaround:
Status:
18.
Problem:
Implication:
Workaround:
Status:
19.
Problem:
Implication:
Workaround:
Status:
Intel® PXA255 Processor Specification Update
Long idle time on external bus between DREQ and nCS for flow-through
DMA.
While observing a flow through DMA transaction, DREQ is asserted, then traffic on the SDRAM
bus finishes, then there is approximately 500ns (50 SDCLKs) of no activity before the chip select
associated with the DMA is asserted. This only occurs once in many DMA transactions.
The problem was that the internal bus arbiter was being retried due to internal buffers being full.
This retry was taking an excessive amount of time.
No Fix
MMC - invalid data can be written to card if user stops then restarts the
clock prior to end of data transfer.
For block writes (single and multiple) it was found that if the user stops the clock and restarts it, say
with a CMD12 programmed to stop the data transfer, the MMC can send out bad data to the card.
This only applies to the case where the clock is stopped/started by writing to the MMC_STRPCL
register, not when the MMC controller stops/starts the clock based on whether the TX fifo has data
in it.
The data corruption does not apply to stream mode writes.
There is no guarantee of the data transfers, response contents, etc. if software turns the clock off
before a command and data sequence is complete.
Software should never turn the clock off before the end of a command protocol and any data
transfer, with the exception of the stop command for stream writes.
No Fix
PMU monitoring event #1, cycles in which the I-cache cannot deliver an
instruction, is incorrectly incremented
The only clock cycles that should be counted for PMU monitoring event #1 are for I-cache misses
or I-TLB misses. Many other events may erroneously cause this counter to increment.
Do not use PMU monitoring event #1.
No Fix
In Special Debug State, back to back memory transactions may hang if the
first memory operation receives a precise data abort.
Special Debug State (SDS) is used by debug vendors. If a back to back store is used in SDS, and
the first store receives a precise data abort, the first memory operation is correctly cancelled, but
the second memory operation may leave the core in an unknown state.
While in SDS, any memory operation that may cause a precise data abort must be followed by a
Drain Write Buffer command. Load Multiple/Store Multiple that may cause precise data aborts
must not be used.
No Fix
Errata
17