LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 20

• Manufacturer Part Number: LUPXA255A0C200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866868

Errata
27.
Problem:
Implication:
Workaround:
Status:
28.
Problem:
Implication:
Workaround:
Status:
29.
Problem:
Implication:
Workaround:
Status:
30.
Problem:
Implication:
Workaround:
Status:
20
Note: Changing the crystal, changes the base frequency to the clock manager and all of the peripherals.
Slow IrDA Transmit pulse width cropped when SET BREAK is used
The Slow IrDA (SIR) port can show errors while transmitting data.
When the UART is transmitting in (SIR) mode a cropped pulse can occur when the Set Break (SB)
bit in the Line Control Register (LCR) is deasserted. This can occur in either XMODE 0 or
XMODE 1 and at any baud rate. A pulse width as low as 0.8us has been seen instead of the
expected 1.6 us XMODE=1 pulse.
Ensure that software does not attempt to disable the Transmitter SIR enable bit (XMITIR) in the
Infrared Selection Register (IRDASEL) and that LCR[SB] is not used while in SIR mode.
No Fix
Fast Infrared FIR mode fails IrDA spec
The IR specification states that Fast Infrared FIR 4Mbits/Sec operates at 8MHz and has a rate
tolerance of .01%. The applications processor has an FIR frequency of 7.98716 MHz which is an
error rate of 0.16% which exceeds the IrDA Serial Infrared Physical Layer Specification, Version
1.4, February 6, 2001.
Systems using FIR mode will not be operating within Version 1.4 of the IrDA Serial Infrared
Physical Layer Specification.
Replace the 3.6864MHz crystal with a 3.69MHz crystal. This crystal frequency change enables the
FIR mode of the applications processor to operate within specification.
Ensure that complete system regression tests are used to validate the workaround.
No Fix
Asserting MBREQ during the MRS command transfer can cause SDRAM
data corruption
When the companion chip asserts the memory bus request MBREQ signal immediately after
deassertion (i.e. for a second time) which then occurs at the same time the Mode Register Set MRS
command is sent to the SDRAM to configure them back to burst of 4, a data corruption of the
SDRAM data is possible. This only occurs if the applications processor is in SA1111 compatibility
mode.
When the companion chip has control of the bus for SDRAM chip select 0, the SDRAM chip
selects 1, 2, and 3 are held in their active low state until the companion chip releases control of the
bus. If they exist, there is a potential for data corruption in the upper three banks of SDRAM.
To avoid SDRAM data corruption, do not re-assert MBREQ for at least 80 memory clocks after the
de-assertion of the previous MBREQ.
No Fix
Invalid AC’97 interrupt during cold reset
Invalid AC’97 interrupt may occur when the ‘cold reset’ bit is set or cleared in the GCR.
A spurious interrupt may occur during a cold reset.
Disable AC’97 interrupts before doing a cold reset by setting GCR[COLD_RST]. When the cold
reset event is complete, the interrupts can be re-enabled.
No Fix
Intel® PXA255 Processor Specification Update