LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 21

• Manufacturer Part Number: LUPXA255A0C200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866868

31.
Problem:
Implication:
Workaround:
Status:
32.
Problem:
Implication:
Workaround:
Status:
Intel® PXA255 Processor Specification Update
GPIO output signals, memory address pins and the memory controls pins,
nOE and nWE, are unpredictable in sleep.
When the PXbus frequency is greater than 133MHz, the states of the GPIO output signals, address
pins and the memory control pins, nOE and nWE, are unpredictable in sleep.
When the PXbus frequency is greater than 133MHz,
1) GPIO signals that are configured as outputs may float.
2) If the FS bit in the PCFR register is set, nOE and nWE may not float during sleep.
3) The address bus pins MA[18:0] may attempt to return to their state for the last transaction.
Depending on how these signals are implemented in a system, this may result in increased power
consumption.
To drive or float these signals as documented during sleep, do a frequency change sequence (FCS)
to a PXbus frequency of 133MHz or less. When the FCS is complete, the CCCR register can be set
back to the original value before entering sleep. This will allow the processor to resume at the
original frequency upon sleep wakeup.
To ensure that the GPIO signals maintain the correct state during sleep, the PGSR registers must be
written with the correct values. This applies to all GPIO pins including those being used as
alternate functions.
To prevent any affected address pins from changing state from low to high during sleep, the last
instruction before the write to the co-processor putting the part to sleep should be a read from
address 0x0.
No Fix
Non-branch instruction in vector table may execute twice after a thumb
mode exception
If an exception occurs in thumb mode and a non-branch instruction is executed at the corre-
sponding exception vector, that instruction may execute twice.
Typically instructions located at exception vectors must be branch instructions which go to the
appropriate handler, but the ARM architecture allows the FIQ handler to be placed directly at the
FIQ vector (0x0000001c/0xffff001c) without requiring a branch. Because of this bug, the first
instruction of such an FIQ handler may be executed twice if it is not a branch instruction.
If a no-op is placed at the beginning of the FIQ handler, the no-op will execute twice and no
incorrect behavior will result. If a branch instruction is placed at the beginning of the handler, it
will not be executed twice.
No Fix
Errata
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