LUPXA255A0C300 Intel, LUPXA255A0C300 Datasheet - Page 17

• Manufacturer Part Number: LUPXA255A0C300
• Description: IC MICRO PROCESSOR 300MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C300

• Processor Type: XScale®
• Speed: 300MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866869

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
nRESET_OUT
JTAG and Test Pins
nTRST
TDI
TDO
TMS
TCK
TEST
TESTCLK
Power and Ground Pins
VCC
VSS
PLL_VCC
PLL_VSS
VCCQ
VSSQ
VCCN
VSSN
Pin Name
Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)
OC
IC
IC
OCZ
IC
IC
IC
IC
SUP
SUP
SUP
SUP
SUP
SUP
SUP
SUP
Type
Reset out. (output) Asserted when nRESET is asserted
and deasserts after nRESET is de-asserted but before
the first instruction fetch. nRESET_OUT is also asserted
for “soft” reset events: sleep, watchdog reset, or GPIO
reset.
JTAG test interface reset. Resets the JTAG/debug port.
If JTAG/debug is used, drive nTRST from low to high
either before or at the same time as nRESET. If JTAG is
not used, nTRST must be either tied to nRESET or tied
low.
JTAG test data input. (input) Data from the JTAG
controller is sent to the PXA255 processor using this pin.
This pin has an internal pull-up resistor.
JTAG test data output. (output) Data from the PXA255
processor is returned to the JTAG controller using this
pin.
JTAG test mode select. (input) Selects the test mode
required from the JTAG controller. This pin has an
internal pull-up resistor.
JTAG test clock. (input) Clock for all transfers on the
JTAG test interface.
Test Mode. (input) Reserved. Must be grounded.
Test Clock. (input) Reserved. Must be grounded.
Positive supply for internal logic. Must be connected
to the low voltage supply on the PCB.
Ground supply for internal logic. Must be connected to
the common ground plane on the PCB.
Positive supply for PLLs and oscillators. Must be
connected to the common low voltage supply.
Ground supply for the PLL. Must be connected to
common ground plane on the PCB.
Positive supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
3.3v supply on the PCB.
Ground supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
ground plane on the PCB.
Positive supply for memory bus and PCMCIA pins.
Must be connected to the common 3.3v or 2.5v supply on
the PCB.
Ground supply for memory bus and PCMCIA pins.
Must be connected to the common ground plane on the
PCB.
Signal Descriptions
Driven low during
any reset sequence
- driven high prior to
first fetch.
Input
Input
Hi-Z
Input
Input
Input
Input
Powered
Grounded
Powered
Grounded
Powered
Grounded
Powered
Grounded
Reset State
Package Information
Driven Low
Input
Input
Hi-Z
Input
Input
Input
Input
Note [6]
Grounded
Note [6]
Grounded
Note [7]
Grounded
Note [7]
Grounded
Sleep State
17