LUPXA255A0E400 Intel, LUPXA255A0E400 Datasheet - Page 10

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LUPXA255A0E400

Manufacturer Part Number
LUPXA255A0E400
Description
IC MICRO PROCESSOR 400MHZ 256BGA
Manufacturer
Intel
Datasheets

Specifications of LUPXA255A0E400

Processor Type
XScale®
Speed
400MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
867749

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Package Information
10
SDCKE[1]
SDCLK[0]
SDCLK[1]
SDCLK[2]
nCS[5]/
GPIO[33]
nCS[4]/
GPIO[80]
nCS[3]/
GPIO[79]
nCS[2]/
GPIO[78]
nCS[1]/
GPIO[15]
nCS[0]
RD/nWR
RDY/
GPIO[18]
L_DD[8]/
GPIO[66]
Pin Name
Table 3.
Pin and Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
OC
OC
OCZ
OC
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
OCZ
ICOCZ
ICOCZ
Type
SDRAM and/or Synchronous Static Memory clock
enable. (output) Connect to the clock enable pins of
SDRAM. It is deasserted during sleep. SDCKE[1] is
always de-asserted upon reset. The memory controller
provides control register bits for de-assertion.
Synchronous Static Memory clock. (output) Connect to
the clock (CLK) pins of SMROM. It is driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide-by-2 clock speed and may be
turned off via free-running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[0] control register assertion bit
defaults to on if the boot-time static memory bank 0 is
configured for SMROM.
SDRAM Clocks (output) Connect SDCLK[1] and
SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide-by-2 clock speed and may be
turned off via free-running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and de-assertion of
each SDCLK pin. SDCLK[2:1] control register assertion
bits are always de-asserted upon reset.
Static chip selects. (output) Chip selects to static
memory devices such as ROM and Flash. Individually
programmable in the memory configuration registers.
nCS[5:0] can be used with variable latency I/O devices.
Static chip select 0. (output) Chip select for the boot
memory. nCS[0] is a dedicated pin.
Read/Write for static interface. (output) Signals that the
current transaction is a read or write.
Variable latency I/O ready pin. (input) Notifies the
memory controller when an external bus device is ready
to transfer data.
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
Memory controller alternate bus master request.
(input) Allows an external device to request the system
bus from the memory controller.
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Signal Descriptions
Driven low
Driven Low
Driven Low
Pulled High -
Note[1]
Driven High
Driven Low
Pulled High -
Note[1]
Pulled High -
Note[1]
Reset State
Driven low
Driven Low
Driven Low
Note [4]
Note [4]
Holds last state
Note [3]
Note [3]
Sleep State

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