PRIXP422BB

Manufacturer Part NumberPRIXP422BB
DescriptionIC NETWRK PROCESSR 266MHZ 492BGA
ManufacturerIntel
PRIXP422BB datasheets
 

Specifications of PRIXP422BB

Processor TypeNetworkFeaturesXScale Core
Speed266MHzVoltage1.3V
Mounting TypeSurface MountPackage / Case492-BGA
Core Operating Frequency533MHzPackage TypeBGA
Pin Count492MountingSurface Mount
Operating Temperature (max)85COperating Temperature (min)-40C
Operating Temperature ClassificationIndustrialLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names869384  
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®
Intel
IXP42X Product Line of Network
Processors and IXC1100 Control Plane
Processor
Product Features
For a complete list of product features, see
®
Intel XScale
Core
Three Network Processor Engines
PCI Interface
Two MII Interfaces
UTOPIA-2 Interface
USB v 1.1 Device Controller
Two High-Speed, Serial Interfaces
SDRAM Interface
Typical Applications
High-Performance DSL Modem
High-Performance Cable Modem
Residential Gateway
SME Router
Network Printers
Datasheet
“Product Features” on page
9.
Encryption/Authentication
High-Speed UART
Console UART
Internal Bus Performance Monitoring Unit
16 GPIOs
Four Internal Timers
Packaging
—492-pin PBGA
—Commercial/Extended Temperature
Control Plane
Integrated Access Device (IAD)
Set-Top Box
Access Points (802.11a/b/g)
Industrial Controllers
Document Number:
252479-004
June 2004

PRIXP422BB Summary of contents

  • Page 1

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Product Features For a complete list of product features, see ® Intel XScale Core ■ Three Network Processor Engines ■ PCI Interface ■ Two MII Interfaces ■ UTOPIA-2 Interface ■ USB v 1.1 Device Controller ■ ...

  • Page 2

    ... Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility applications. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them ...

  • Page 3

    ... High-Speed and Console UARTs ..........................................................................22 2.1.11 GPIO ......................................................................................................................22 2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) ..............................................22 2.1.13 Interrupt Controller .................................................................................................22 2.1.14 Timers ....................................................................................................................23 2.1.15 AHB Queue Manager ............................................................................................23 ® 2.2 Intel XScale Core..............................................................................................................23 2.2.1 Super Pipeline .......................................................................................................24 2.2.2 Branch Target Buffer (BTB) ...................................................................................25 2.2.3 Instruction Memory Management Unit (IMMU) ......................................................26 2 ...

  • Page 4

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Contents 5.0 Electrical Specifications ............................................................................................................. 74 5.1 Absolute Maximum Ratings ................................................................................................ 74 5 CCPLL1 CCPLL2 5.2.1 V Requirement ............................................................................................ 74 CCPLL1 5.2.2 V Requirement ............................................................................................ 75 CCPLL2 5.2.3 V Requirement .......................................................................................... 75 CCOSCP 5.2.4 V Requirement ............................................................................................ 76 CCOSC 5.3 RCOMP Pin Requirements................................................................................................. 77 5.4 DC Specifications ............................................................................................................... 77 5.4.1 Operating Conditions ............................................................................................. 77 5 ...

  • Page 5

    ... MDIO Output Timings .................................................................................................................91 22 MDIO Input Timings....................................................................................................................91 23 SDRAM Input Timings ................................................................................................................92 24 SDRAM Output Timings .............................................................................................................93 25 Intel Multiplexed Mode................................................................................................................93 26 Intel Simplex Mode .....................................................................................................................94 27 Motorola* Multiplexed Mode .......................................................................................................95 28 Motorola* Simplex Mode.............................................................................................................97 29 HPI – 8 Mode Write Accesses ....................................................................................................99 30 HPI-16 Multiplex Write Mode ....................................................................................................101 31 HPI-16 Multiplex Read Mode ...

  • Page 6

    ... Power Interface .......................................................................................................................... 41 19 Part Numbers ............................................................................................................................. 43 20 Ball Map Assignment for the Intel 21 Ball Map Assignment for the Intel 22 Ball Map Assignment for the Intel 23 Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor ............................................................................. 66 24 Operating Conditions .................................................................................................................. 77 25 PCI DC Parameters .................................................................................................................... 78 26 USB v1 ...

  • Page 7

    ... MDIO Timings Values.................................................................................................................92 50 SDRAM Input Timings Values ....................................................................................................92 51 SDRAM Output Timings Values .................................................................................................93 52 Intel Multiplexed Mode Values....................................................................................................94 53 Intel Simplex Mode Values .........................................................................................................95 54 Motorola* Multiplexed Mode Values ...........................................................................................96 55 Motorola* Simplex Mode Values.................................................................................................98 56 HPI Timing Symbol Description ..................................................................................................99 57 HPI – 8 Mode Write Accesses Values ........................................................................................99 58 Setup/Hold Timing Values ...

  • Page 8

    ... Intel 003 Network Processors and IXC1100 Control Plane Processor Specification Update (252702-003). Incorporated specification changes, specification clarifications and document changes from the Intel Network Processors Specification Update (252702-001). 002 Incorporated information for the Intel Processor. Initial release of this document. Document reissued, without 001 “ ...

  • Page 9

    ... Table 1 on page 12 Processors and IXC1100 Control Plane Processor. • ® Intel XScale — High-performance processor based on Intel XScale — Seven/eight-stage Intel — Management unit • 32-entry, data memory management unit • 32-entry, instruction memory management unit • 32-Kbyte, 32-way, set associative instruction cache • ...

  • Page 10

    ... Programmable auto-refresh — Programmable CAS/data delay — Support for 8 MB, minimum 256 MB maximum • Expansion interface — 24-bit address — 16-bit data — Eight programmable chip selects — Supports Intel/Motorola* microprocessors • Multiplexed-style bus cycles • Simplex-style bus cycles 10 Datasheet ...

  • Page 11

    ... Monitoring of internal bus occurrences and duration events • 16 GPIOs • Four internal timers • Packaging — 492-pin PBGA — Commercial temperature (0° to +70° C) — Extended temperature (-40° to +85° C) Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Product Features 11 ...

  • Page 12

    ... Only the 266-MHz version of the Intel 1.3 About this Document This datasheet contains a functional overview of the Intel Processors and IXC1100 Control Plane Processor, as well as mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications, and some bus functional wave forms for the device. Detailed functional descriptions — other than parametric performance — ...

  • Page 13

    ... IXP4XX Product Line Programmer’s Guide (Version 1.1) ® Intel XScale™ Core Developer’s Manual ® Intel IXP4XX Product Line and Intel ® Intel XScale Microarchitecture Technical Summary PCI Local Bus Specification, Rev. 2.2 Universal Serial Bus Specification, Revision 1.1 ...

  • Page 14

    ... IXC1100 control plane processors are designed with Intel state-of-the-art 0.18-µ production semiconductor process technology. This process technology — along with the compactness of the Intel XScale core, the ability to simultaneously process up to three integrated network processing engines (NPEs), and numerous dedicated-function peripheral interfaces — ...

  • Page 15

    ... High-Performance Bus Ethernet NPE A Arbiter Ethernet MAC Bridge Arbiter Bridge 133 MHz Advanced High- Performance Bus PMU ® Intel XScale Core (AHB) 266 MHz 32 KB Data Cache Test Logic Unit 32 KB Instruction Cache 2 KB Mini-Data Cache JTAG Functional Overview Queue Status ...

  • Page 16

    ... MHz Advanced High-Performance Bus Ethernet NPE B Arbiter Ethernet MAC Bridge Arbiter Bridge 133 MHz Advanced High- Performance Bus PMU Intel XScale ® Core (AHB) 266/400/533 MHz 32 KB Data Cache Test Logic Unit 32 KB Instruction Cache 2 KB Mini-Data Cache JTAG Queue Status ...

  • Page 17

    ... The network processor engines (NPEs) are dedicated-function processors containing hardware coprocessors integrated into the IXP42X product line and IXC1100 control plane processors. The NPEs are used to off-load processing functions required by the Intel XScale core. These NPEs are high-performance, hardware-multi-threaded processors with additional local-hardware-assist functionality used to off-load highly processor-intensive functions such as MII (MAC), CRC checking/generation, AAL 2, AES, DES, SHA-1, and MD5 ...

  • Page 18

    ... The combined forces of the hardware multi-threading, local-code store, independent instruction memory, independent data memory, and parallel processing allows the Intel XScale core to be utilized for application purposes. The multi-processing capability of the peripheral interface functions allows unparalleled performance to be achieved by the application running on the Intel XScale core. 2.1.2 ...

  • Page 19

    ... NPEs on the North AHB and the SDRAM. 2.1.2.2 South AHB The South AHB is a 133.32-MHz, 32-bit bus that can be mastered by the Intel XScale controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the SDRAM, PCI interface, queue manager, expansion bus, or the APB/AHB bridge. ...

  • Page 20

    ... PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable of operating as either a host or an option (i.e. not the Host) For more information on PCI Controller support and configuration see the Intel Control Plane Processor Developer’s Manual 2 ...

  • Page 21

    ... It also provides input information for device configuration after reset. Some of the peripheral device types are flash, ATM control interfaces, and DSPs used for voice applications. (Some voice configurations can be supported by the HSS interfaces and the Intel XScale implementing voice-compression algorithms.) The expansion bus interface is a 16-bit interface that allows an address range of 512 bytes to 16 Mbytes, using 24 address lines for each of the eight independent chip selects ...

  • Page 22

    ... Interrupt Controller The IXP42X product line and IXC1100 control plane processors consists of 32 interrupt sources to allow an extension of the Intel XScale originate from some external GPIO pins or internal peripheral interfaces. The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled. The interrupt sources tied to Interrupt can be prioritized ...

  • Page 23

    ... The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the NPEs and Intel XScale core (or any other AHB bus master), a Flag Bus interface, an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale core. The AHB interface is used for configuration of the AQM and provides access to queues, queue status and SRAM ...

  • Page 24

    ... Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of internal bus performance. • JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-change messages) to debug programs ® ...

  • Page 25

    ... Successfully predicted branches avoid any branch-latency penalties in the super pipeline. Unsuccessfully predicted branches result in a four to five cycle branch-latency penalty in the super pipeline. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor • • Weakly taken Weakly not taken Functional Overview • ...

  • Page 26

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview 2.2.3 Instruction Memory Management Unit (IMMU) For instruction pre-fetches, the IMMU controls logical-to-physical address translation, memory access permissions, memory-domain identifications, and attributes (governing operation of the instruction cache). The IMMU contains a 32-entry, fully associative instruction-translation, look-aside buffer (ITLB) that has a round-robin replacement policy ...

  • Page 27

    ... The mini-data cache (together with the D-cache) can be enabled or disabled. Attribute bits contained within a coprocessor register specify operating modes write and/or read allocate, write-back, and write-through. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview 27 ...

  • Page 28

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Functional Overview The mini-data cache (and D-cache) work with the load buffer and pend buffer to provide “hit-under-miss” capability that allows the core to access other data in the cache after a “miss” is encountered ...

  • Page 29

    ... The debug unit — when used with debugger application code running on a host system outside of the Intel XScale core — allows a program, running on the Intel XScale core debugged. It allows the debugger application code or a debug exception to stop program execution and redirect execution to a debug-handling routine ...

  • Page 30

    ... Listed in the signal definition tables — starting at pull-up an pull-down resistor recommendations that are required when the particular enabled interface is not being used in the application. These external resistor requirements are only needed if the particular model of Intel the particular interface enabled and the interface is not required in the application. Warning: All IXP42X product line and IXC1100 control plane processors I/O pins are not 5-V tolerant ...

  • Page 31

    ... Table 5. SDRAM Interface (Sheet Name SDM_ADDR[12:0] SDM_DATA[31:0] SDM_CLKOUT SDM_BA[1:0] SDM_RAS_N SDM_CAS_N SDM_CS_N[1:0] SDM_WE_N † For a legend of the Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor signals signals signals signals signals signals signals signals signals signals signals signals signals ...

  • Page 32

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Functional Signal Descriptions Table 5. SDRAM Interface (Sheet Power Name on Reset SDM_CKE SDM_DQM[3:0] † For a legend of the 32 † † Reset Type † SDRAM Clock Enable: CKE is driving high to activate the clock to an ...

  • Page 33

    ... PCI_SERR_N PCI_DEVSEL_N PCI_IDSEL PCI_REQ_N[3:1] PCI_REQ_N[0] PCI_GNT_N[3:1] † For a legend of the Type codes, see Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Power † † On Reset Type † PCI Address/Data bus used to transfer address and bidirectional data to and from multiple PCI devices. ...

  • Page 34

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Functional Signal Descriptions Table 6. PCI Controller (Sheet Power On Name Reset PCI_GNT_N[0] PCI_INTA_N PCI_CLKIN For a legend of the Type codes, see † Table 7. High-Speed, Serial Interface 0 Power Name Reset HSS_TXFRAME0 HSS_TXDATA0 HSS_TXCLK0 HSS_RXFRAME0 ...

  • Page 35

    ... MII Interfaces (Sheet Name ETH_TXCLK0 ETH_TXDATA0[3:0] ETH_TXEN0 ETH_RXCLK0 † For a legend of the Type codes, see Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Power † On † Reset Type † Reset The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to allow an external source to be synchronized with the transmitted data ...

  • Page 36

    ... Management data clock. Management data interface clock is used to clock the MDIO signal as an output and sample the MDIO as an input The ETH_MDC is an input on power up and can be configured output through an Intel API as documented in the Intel Software Programmer’s Guide. Externally supplied transmit clock. • 25 MHz for 100-Mbps operation Z ...

  • Page 37

    ... UTP_OP_SOC UTP_OP_DATA[7:0] UTP_OP_ADDR[4:0] UTP_OP_FCI UTP_IP_CLK UTP_IP_FCI UTP_IP_SOC † For a legend of the Type codes, see Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Power † † On Reset Type † Reset UTOPIA Transmit clock input. Also known as UTP_TX_CLK. This signal is used to synchronize all UTOPIA-transmit outputs to the rising edge of the UTP_OP_CLK ...

  • Page 38

    ... TI*-mode data strobe (TI_HDS1_N). Intel-mode read strobe / Motorola-mode read-not-write (EXPB_MOT_RNW mode read-not-write (TI_HR_W_N). External chip selects for expansion bus. • Chip selects 0 through 7 can be configured to support Intel Motorola bus cycles. • Chip selects 4 through 7 can be configured to support TI HPI bus cycles. ...

  • Page 39

    ... Table 13. USB Interface Name USB_DPOS USB_DNEG † For a legend of the Type codes, see Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor † † Reset Type UART serial data input to High-Speed UART Pins Should be pulled low through a 10-KΩ resistor when not being utilized in the system ...

  • Page 40

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Functional Signal Descriptions Table 14. Oscillator Interface Power Name On † Reset OSC_IN OSC_OUT † For a legend of the Type codes, see Table 15. GPIO Interface Power Name On † Reset GPIO[12:0] Z GPIO[13] Z GPIO[14] Z GPIO[15] Z † ...

  • Page 41

    ... VCCOSCP I VSSOSCP I VCCOSC I VSSOSC I VCCPLL1 I VCCPLL2 I † For a legend of the Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Power † † On Reset Type † Reset Used for test purposes only Must be pulled high for normal operation. Used for test purposes only. ...

  • Page 42

    ... Package and Pinout Information ® The Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor have a 492-ball, plastic ball grid array (PBGA) package for commercial-temperature applications and a pin-for-pin, compatible 492-ball, plastic ball grid array with a drop-in heat spreader (H) for extended-temperature applications ...

  • Page 43

    ... IXP422 Network Processor ® Intel IXP421 Network Processor Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor i FWIXP42 XBX <FPO> INTEL M C 2002 <ATPO> YWW KOREA Speed Stepping Part # (MHz) B-0 533 FWIXP425BD B-0 400 FWIXP425BC B-0 266 FWIXP425BB ...

  • Page 44

    ... Processor ® Intel IXP420 Network Processor ® Intel IXC1100 Control Plane Processor ® Intel IXC1100 Control Plane Processor ® Intel IXC1100 Control Plane Processor ® Intel IXC1100 Control Plane Processor ® Intel IXC1100 Control Plane Processor ® Intel IXC1100 Control Plane ...

  • Page 45

    ... Intel IXP425 Network Processor ® Intel IXP422 Network Processor ® Intel IXP421 Network Processor ® Intel IXP420 Network Processor ® and Intel IXC1100 Control Plane Processor Table 20. Ball Map Assignment for the Intel Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 ...

  • Page 46

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 20. Ball Map Assignment for the Intel Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 ...

  • Page 47

    ... Table 20. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and ...

  • Page 48

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 20. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 ...

  • Page 49

    ... Table 20. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 HSS_TXDATA0 U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and ...

  • Page 50

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 20. Ball Map Assignment for the Intel Ball Signal AA1 HSS_RXDATA0 AA2 VCCP AA3 VSS AA4 HSS_RXCLK1 AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 ETH_TXDATA1[1] ...

  • Page 51

    ... Table 20. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP AE6 ETH_RXDV1 AE7 VSS AE8 ETH_COL1 AE9 VCCP AE10 VCCPLL1 AE11 VSS AE12 VCCPLL2 AE13 VCCP AE14 UTP_OP_DATA[5] AF14 AE15 VSS AE16 ...

  • Page 52

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 21. Ball Map Assignment for the Intel Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 SDM_DATA[13] A11 SDM_DATA[11] A12 SDM_DATA[10] A13 SDM_DATA[6] A14 ...

  • Page 53

    ... Table 21. Ball Map Assignment for the Intel Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 SDM_DQM[0] E15 VCCP E16 SDM_BA[0] E17 VSS E18 SDM_ADDR[7] E19 VCCP E20 SDM_ADDR[3] E21 ...

  • Page 54

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 21. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors ...

  • Page 55

    ... Table 21. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VCC N23 VSS N24 VCC N25 EX_DATA[4] N26 EX_DATA[5] NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and ...

  • Page 56

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 21. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 N/C U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors ...

  • Page 57

    ... Table 21. Ball Map Assignment for the Intel Ball Signal AA1 N/C AA2 VCCP AA3 VSS AA4 N/C AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 ETH_TXDATA1[1] AA10 VCC AA17 VCC AA18 N/C AA19 N/C AA20 VSS AA21 VCC AA22 TXDATA1 ...

  • Page 58

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 21. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP AE6 ETH_RXDV1 AE7 VSS AE8 ETH_COL1 AE9 VCCP ...

  • Page 59

    ... Table 22. Ball Map Assignment for the Intel Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 SDM_DATA[13] A11 SDM_DATA[11] A12 SDM_DATA[10] A13 SDM_DATA[6] A14 SDM_DATA[8] A15 SDM_DQM[1] A16 SDM_CS_N[0] A17 SDM_CLKOUT A18 SDM_RAS_N A19 SDM_ADDR[12] A20 SDM_ADDR[9] A21 ...

  • Page 60

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 22. Ball Map Assignment for the Intel Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 ...

  • Page 61

    ... Table 22. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and ...

  • Page 62

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 22. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 ...

  • Page 63

    ... Table 22. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 HSS_TXDATA0 U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] NOTE: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and ...

  • Page 64

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 22. Ball Map Assignment for the Intel Ball Signal AA1 HSS_RXDATA0 AA2 VCCP AA3 VSS AA4 HSS_RXCLK1 AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 N/C ...

  • Page 65

    ... Table 22. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 N/C AE5 VCCP AE6 N/C AE7 VSS AE8 N/C AE9 VCCP AE10 VCCPLL1 AE11 VSS AE12 VCCPLL2 AE13 VCCP AE14 UTP_OP_DATA[5] AF14 AE15 VSS AE16 ...

  • Page 66

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 23. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 ...

  • Page 67

    ... Table 23. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 SDM_DQM[0] E15 VCCP E16 SDM_BA[0] E17 ...

  • Page 68

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 23. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] ...

  • Page 69

    ... Table 23. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VCC N23 VSS N24 VCC N25 ...

  • Page 70

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 23. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 N/C U6 VCC U21 VCC U22 GPIO[14] ...

  • Page 71

    ... Table 23. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal AA1 N/C AA2 VCCP AA3 VSS AA4 N/C AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 ETH_TXDATA1[1] AA10 VCC AA17 VCC AA18 N/C ...

  • Page 72

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Package and Pinout Information Table 23. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP ...

  • Page 73

    ... Using the preceding junction-temperature formula, the extended temperature for a 533-MHz part — assuming a maximum power of 2.4 W — would be 115° (0. 114.23° Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor is proportional to the temperature difference JT” which is the thermal resistance from the device jc, Ψ * Power Dissipation Power Dissipation) Ψ ...

  • Page 74

    ... CCPLL1 CCPLL2 To reduce voltage-supply noise on the analog sections of the Intel Network Processors and IXC1100 Control Plane Processor, the phase-lock loop circuits ( and oscillator circuit (V CCPLL2 The filter circuits for each supply are shown in the following sections. ...

  • Page 75

    ... IXC1100 Control Plane V SS Processor B1680-02 CCPLL2 supply pin. Both capacitors SS pin and the associated V pin CCPLL2 Intel ® IXP4XX Product Line / Intel ® IXC1100 Control Plane V Processor SS B1681-02 pin and V pin of the CCP_OSC SSP_OSC consists of two pins, SSP_OSC Figure 10. pin ...

  • Page 76

    ... SSOSCP SS CCOSC 10 nF 100 nF 100 Intel ® IXP4XX Product Line / ® Intel IXC1100 Control Plane Processor B1675-03 supply pin. Both capacitors SSOSC pin and the associated V pin. SSOSC Intel ® IXP4XX Product Line / Intel ® IXC1100 Control Plane Processor B1676-02 Datasheet ...

  • Page 77

    ... Voltage supplied to the analog phase-lock V CCPLL2 loop. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor RCOMP ® Intel IXP4XX Product Line / 34 Ω, ® Intel IXC1100 Control Plane + Parameter Min. 3.135 1.235 1.235 3.135 1.235 1.235 Electrical Specifications ...

  • Page 78

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications PCI DC Parameters 5.4.2 Table 25. PCI DC Parameters Symbol Parameter V Input-high voltage IH V Input-low voltage IL V Output-high voltage OH V Output-low voltage OL I Input-leakage current IL C Input-pin capacitance IN I/O or output pin C OUT ...

  • Page 79

    ... Output current at low I OL voltage I Input-leakage current IL C Input-pin capacitance IN NOTES: 1. These values are typical values seen by the manufacturing process and are not tested. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Parameter Conditions OUT OUT V > 2 < 0 < ...

  • Page 80

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications 5.4.6 MDIO DC Parameters Table 29. MDIO DC Parameters Symbol Parameter V Input-high voltage IH V Input-low voltage IL V Output-high voltage OH V Output-low voltage OL I Input-leakage current IL C Input-pin capacitance IN C Input-pin capacitance INMDIO NOTES: 1 ...

  • Page 81

    ... V Output-low voltage OL I Input-leakage current IL C Input-pin capacitance IN NOTES: 1. These values are typical values seen by the manufacturing process and are not tested. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Parameter Conditions OUT I = 4mA OUT 0 < V < CCP ...

  • Page 82

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications High-Speed and Console UART DC Parameters 5.4.11 Table 34. UART DC Parameters Symbol Parameter V Input-high voltage IH V Input-low voltage IL V Output-high voltage OH V Output-low voltage OL I Input-leakage current IL C Input-pin capacitance IN NOTES: 1 ...

  • Page 83

    ... These values are typical values seen by the manufacturing process and are not tested. 5.4.14 Reset DC Parameters Table 37. PWRON_Reset _N DC Parameters Symbol V Input-high voltage IH V Input-low voltage IL I Input leakage current IL C Input Capacitance IN Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Parameter Conditions = I OUT OUT OUT OUT 0 < Parameter Conditions ...

  • Page 84

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications 5.5 AC Specifications 5.5.1 Clock Signal Timings 5.5.1.1 Processor Clock Timings Device Clock Timings Table 38. Symbol V Input-high voltage IH V Input-low voltage IL Clock frequency for IXP42X product line T and IXC1100 control plane processors FREQUENCY crystal or oscillator ...

  • Page 85

    ... Reference) (Sheet Parameter Min. 35 Intel ® IXP4XX Product Line / Intel ® IXC1100 Control Plane Processor OSC_IN C 1 XTAL OSC_OUT C 2 Intel ® IXP4XX Product Line / ® Intel IXC1100 Control Plane Processor OSC_IN Oscillator OSC_OUT Electrical Specifications Nom. Max. Units Notes B1677-02 B1678-02 85 ...

  • Page 86

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications 5.5.1.2 PCI Clock Timings Table 40. PCI Clock Timings Symbol T Clock period for PCI Clock PERIODPCICLK T PCI Clock high time CLKHIGH T PCI Clock low time CLKLOW Rise and fall time ...

  • Page 87

    ... The AC timing waveforms are shown in the following sections. 5.5.2.1 PCI Figure 15. PCI Output Timing CLK Output Delay NOTE 0 Figure 16. PCI Input Timing CLK Input Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor T clk2out(b) and LOW CC T setup(b) Electrical Specifications low A9572-01 ...

  • Page 88

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications Table 44. PCI Bus Signal Timings Symbol Clock to output for all bused signals. This is the PCI_AD[31:0], PCI_CBE_N [3:0], PCI_PAR, T PCI_FRAME_N, PCI_IRDY_N, clk2outb PCI_TRDY_N, PCI_STOP_N, PCI_DEVSEL_N, PCI_PERR_N, PCI_SERR_N Clock to output for all point-to-point T signals ...

  • Page 89

    ... Outputs included in this timing are T UTP_IP_DATA[3:0], UTP_OP_SOC, holdout UTP_OP_FCO, UTP_IP_FCO, UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0]. NOTES: 1. Timing was tested with a 70-pF capacitor to ground. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Tsetup Thold Parameter Tclk2out Parameter Electrical Specifications A9578-01 Min. ...

  • Page 90

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications 5.5.2.4 MII Figure 19. MII Output Timings eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs Table 47. MII Output Timings Values Symbol Clock to output delay for ETH_TXDATA and T 1 ETH_TXEN. ETH_TXDATA and ETH_TXEN hold time after ...

  • Page 91

    ... MDIO Figure 21. MDIO Output Timings ETH_MDC ETH_MDIO NOTE: Processor is Sourcing MDIO. Figure 22. MDIO Input Timings ETH_MDC ETH_MDIO NOTE: PHY is sourcing MDIO. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications A9582- A9583-02 91 ...

  • Page 92

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications Table 49. MDIO Timings Values Symbol ETH_MDIO, clock to output timing with respect to T1 rising edge of ETH_MDC clock ETH_MDIO output hold timing after the rising T2 edge of ETH_MDC clock ETH_MDIO input setup prior to rising edge of ...

  • Page 93

    ... Signal output hold time after the rising edge of T the clock. Outputs included in this timing are holdout SDM_DQ[31:0] (during a write operation). NOTES: 1. Timing test were performed with a 70-pF load to ground. 5.5.2.7 Expansion Bus Figure 25. Intel Multiplexed Mode EX_CLK EX_CS_N EX_ADDR EX_ALE EX_WR_N EX_DATA EX_RD_N EX_DATA Datasheet ® ...

  • Page 94

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications Table 52. Intel Multiplexed Mode Values Symbol Talepulse Pulse width of ALE (ADDR is valid at the rising edge of ALE) Tale2addrhold Valid address hold time after from falling edge of ALE Tdval2valwrt Write data valid prior to WR_N falling edge ...

  • Page 95

    ... Table 53. Intel Simplex Mode Values Symbol Parameter T Valid address to valid chip select addr2valcs T Write data valid prior to EXPB_IO_WRITE_N falling edge dval2valwrt T Pulse width of the EXP_IO_WRITE_N wrpulse T Valid data after the rising edge of EXPB_IO_WRITE_N dholdafterwr Data valid required before the rising edge of ...

  • Page 96

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications Table 54. Motorola* Multiplexed Mode Values Symbol Parameter T Pulse width of ALE (ADDR is valid at the rising edge of ALE) alepulse T Valid address hold time after from falling edge of ALE ale2addrhold T Write data valid prior to EXP_MOT_DS_N falling edge ...

  • Page 97

    ... EX_CLK EX_CS_N EX_ADDR EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor T1 T2 1-4 Cycles 1-4 Cycles 1-16 Cycles T ad2valcs Valid Address T dval2valds Electrical Specifications 1-4 Cycles 1-16 Cycles ...

  • Page 98

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications Table 55. Motorola* Simplex Mode Values Symbol Parameter T Valid address to valid chip select ad2valcs T Write data valid prior to EXP_MOT_DS_N falling edge dval2valds T Pulse width of the EXP_MOT_DS_N dspulse T Valid data after the rising edge of EXP_MOT_DS_N ...

  • Page 99

    ... Data valid prior to the rising edge of the HDS1 data T data_setup strobe. T Data valid after the rising edge of the HDS1 data strobe. data_hold Time required between successive accesses on the T recov expansion interface. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Trecov Tadd_setup Valid Thds1_pulse Tdata_hold ...

  • Page 100

    ... The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel ® Line and Intel ...

  • Page 101

    ... The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel ® Line and Intel ...

  • Page 102

    ... The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel ® Line and Intel ...

  • Page 103

    ... Figure 31. HPI-16 Multiplex Read Mode EX_CLK EX_CS_N (hcs_n) EX_ADDR[2:1] (hcntl) EX_RD_N (hr_w_n) Tcs2hds1val EX_WR_N (hds1_n) EX_RDY_N (hrdy) EX_DATA (hdout) Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Tadd_setup Valid Thds1_pulse Tdata_setup Valid Data Electrical Specifications Trecov Valid Data ...

  • Page 104

    ... The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel ® Line and Intel ...

  • Page 105

    ... The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel ® Line and Intel ...

  • Page 106

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications Figure 33. HPI-16 Non-Multiplex Write Mode EX_CLK EX_CS_N (hcs_n) _ADDR[23:0] (ha) EX_RD_N (hr_w_n) Tcs2hds1val EX_W R_N (hds1_n) EX_RDY_N (hrdy) EX_DATA (hdin) 106 Tadd_setup Valid Thds1_pulse Tdata_hold Tdata_setup Data Trecov Valid Data ...

  • Page 107

    ... As Outputs: hss_(tx or rx)frame (Positive edge) hss_(tx or rx)frame (Negative edge) hss_ txdata (Positive edge) hss_ txdata (Negative edge) Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Valid Data Valid Data Valid Data Valid Data Electrical Specifications ...

  • Page 108

    ... KHz. The maximum clock speed that can be accepted or driven is 8.192 MHz. The clock duty cycle accepted will be 50/50 + 20%. 6. Timing tests were performed with a 70-pF capacitor to ground and a 10-K Ω pull-up resistor. For more information on the HSS Jitter Specifications see the Intel Network Processors and IXC1100 Control Plane Processor Developer’s Manual 108 Parameter Min ...

  • Page 109

    ... JTAG_TMS hold time from rising T bsrh edge of JTAG_TRST_N NOTES: 1. Tests completed with a TBD pF load to ground on JTAG_TDO. 2. JTAG_TCK may be stopped indefinitely in either the low or high phase. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor T bsel JTG_TCK T bsis JTG_TDO T bsoh ...

  • Page 110

    ... Intel IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications 5.5.3 Reset Timings Figure 37. Reset Timings V CCP V CC PLL_LOCK PWRON_RESET_N RESET_IN_N EX_ADDR[23:0] EX_ADDR[23:0]-Pull Up/Down 110 CFG Settings To Be Captured CFG Settings To Be Captured RELEASE_RST_N PLL_LOCK RELEASE_PWRON_RST_N T EX_ADDR_SETUP IXP4XX/IXC1100 Drives Outputs ...

  • Page 111

    ... V at 3.3 V and V CCP line and IXC1100 control plane processors. Datasheet ® Intel IXP42X Product Line and IXC1100 Control Plane Processor Parameter Minimum time required to hold the PWRON_RST_N at logic 0 state after stable power has been applied to the IXP42X product line and IXC1100 control plane processors. When using a crystal to drive the processors’ ...

  • Page 112

    ... I/O supply current Total average power Core supply current I/O supply current Total average power Core supply current I/O supply current Total average power and I are not tested. Typical currents were measured on the Intel CCP =1.327V 3.363 V. CC CCP = 1.365 3.465 ...