NHPXA270C5C416 Intel, NHPXA270C5C416 Datasheet
NHPXA270C5C416
Specifications of NHPXA270C5C416
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NHPXA270C5C416 Summary of contents
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... Operating-system timers LCD Controller Universal Subscriber Identity Module interface Data Sheet Low power: — Wireless Intel Speedstep® Technology — Less than 500 mW typical internal dissipation — Supply voltage may be reduced to 0.85 V — Four low-power modes — Dynamic voltage and frequency ...
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... Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ...
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... Internal Power Domains ................................................................5-6 32.768-kHz Oscillator Specifications .............................................5-9 13.000-MHz Oscillator Specifications..........................................5-11 Power-On Timing Specifications ...................................................6-2 Hardware Reset Timing.................................................................6-4 Watchdog Reset Timing ................................................................6-5 GPIO Reset Timing .......................................................................6-5 Sleep Mode Timing .......................................................................6-6 Deep-Sleep Mode Timing..............................................................6-7 Intel® PXA270 Processor Contents iii ...
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... PBGA Intel® PXA270 Processor Package (Top View) ....................3-4 3-6 23x23 mm PBGA Intel® PXA270 Processor Package (Bottom View) ...............3-4 3-7 23x23 mm PBGA Intel® PXA270 Processor Package (Side View) ...................3-5 3-8 PBGA Product Information Decoder ..................................................................3-5 3-9 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view ...............3-6 3-10 Intel® ...
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... Typical External 13.000-MHz Oscillator Requirements....................................5-12 5-13 CLK_PIO Specifications ...................................................................................5-12 5-14 CLK_TOUT Specifications ...............................................................................5-12 5-15 48 MHz Output Specifications ..........................................................................5-13 6-1 Standard Input, Output, and I/O-Pin AC Operating Conditions ..........................6-1 6-2 Power-On Timing Specifications (OSCC[CRI ............................................6-3 Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Contents v ...
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... Intel® PXA270 Processor Contents 6-3 Hardware Reset Timing Specifications (OSCC[CRI ..................................6-4 6-4 Hardware Reset Timing Specifications (OSCC[CRI .................................6-5 6-5 GPIO Reset Timing Specifications .....................................................................6-6 6-6 Sleep-Mode Timing Specifications .....................................................................6-7 6-7 Deep-Sleep Mode Timing Specifications ...........................................................6-8 6-8 GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode .................................6-9 6-9 Standby-Mode Timing Specifications ...
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... April 2004 June 2004 June 2004 Electrical, Mechanical, and Thermal Specification Revision -001 First public release of the EMTS -002 Added 23x23 mm 360-ball PBGA package Added 624-MHz active and idle power consumption values to -003 Table 5-7. Intel® PXA270 Processor Contents Description vii ...
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... Intel® PXA270 Processor Contents viii Electrical, Mechanical, and Thermal Specification ...
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... The Intel® PXA270 processor (PXA270 processor) provides industry-leading multimedia performance, low-power capabilities, rich peripheral integration and second generation memory stacking. Designed from the ground up for wireless clients, it incorporates the latest Intel advances in mobile technology over its predecessor, the Intel® PXA255 processor. These same attributes and features also make the PXA270 processor ideal for embedded applications ...
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... To set a bit, write 0b1 to it. 1.1.3 Applicable Documents Table 1-1 lists supplemental information sources for the PXA270 processor. Contact an Intel representative for the latest document revisions and ordering instructions. Table 1-1. Supplemental Documentation Document Title Intel® ...
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... The Intel® PXA270 processor is an integrated system-on-a-chip microprocessor for high performance, dynamic, low-power portable handheld and hand-set devices as well as embedded platforms. It incorporates the Intel XScale® technology which complies with the ARM* version 5TE instruction set (excluding floating-point instructions) and follows the ARM* programmer’s model. The PXA270 processor also provides Intel® ...
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... Intel® PXA270 Processor Functional Overview Figure 2-1. Intel® PXA270 Processor Block Diagram, Typical System RTC RTC OS Timers OS Tim ers 4 x PWM 4 x PWM Interrupt Interrupt Controller C ontrolle SSP 3 x SSP USIM U SIM AC97 AC 97 DMA Full Function DMA Full Function ...
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... The PXA270 processor is offered in two packages. The 13- by 13-mm, 356-ball, 0.50-mm VF- BGA molded matrix array package is shown in 23-mm, 360-ball, 1.0-mm PBGA molded matrix array package is shown in and Figure 3-7. 3.1 Package Information Figure 3-1. 13x13mm VF-BGA Intel® PXA270 Processor Package, top view A1 Corner Electrical, Mechanical, and Thermal Specification Figure 3- ...
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... Intel® PXA270 Processor Package Information Note: Figure 3-2 and Figure 3-3 Figure 3-2. 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view A B 3-2 show all dimensions in millimeters (mm ø0.30±0.05 (356) 11.50 13±0.10 Electrical, Mechanical, and Thermal Specification 0.50 ...
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... Figure 3-3. 13x13mm VF-BGA Intel® PXA270 Processor Package, side view C Figure 3-4. VF-BGA Product Information Decoder R Package Type LV=Leaded RC=Lead-Free Intel XScale® Family Product Family Member 270=Discrete product Electrical, Mechanical, and Thermal Specification SEATING PLANE Intel® PXA270 Processor ...
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... Package Information Note: Figure 3-5, Figure 3-6 Figure 3-5. 23x23 mm PBGA Intel® PXA270 Processor Package (Top View) A1 CORNER Figure 3-6. 23x23 mm PBGA Intel® PXA270 Processor Package (Bottom View) 1.00 1.00 3-4 and Figure 3-7 show all dimensions in millimeters (mm). ...
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... Figure 3-7. 23x23 mm PBGA Intel® PXA270 Processor Package (Side View) Figure 3-8. PBGA Product Information Decoder F Package Type FW = Leaded NH = Lead-Free Intel XScale® Family Product Family Member 270 = Discrete product Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Package Information // 0 ...
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... Intel® PXA270 Processor Package Information 3.2 Processor Materials Figure 3-9. 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view Table 3-1 describes the basic material properties of the processor components. 3-6 Electrical, Mechanical, and Thermal Specification ...
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... A Pb-Free (lead-free) package is indicated by the letter “E” on the 3rd line of information (Intel legal line). The “E” appears after the date stamp. Figure 3-10. Intel® PXA270 Processor Production Markings, (Laser Mark on Top Side) Electrical, Mechanical, and Thermal Specification ...
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... Intel® PXA270 Processor Package Information 3.5 Tray Drawing For tray drawing information, refer to the Intel Developer website for the Intel® Wireless Communications and Computing Package Users Guide. 3-8 §§ Electrical, Mechanical, and Thermal Specification ...
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... Pin Listing and Signal Definitions This chapter describes the signals and pins for the Intel® PXA270 processor. For descriptions of all PXA270 processor signals, refer to the “System Architecture” chapter in the Intel® PXA27x Processor Family Developer’s Manual. Table 4-2 lists the mapping of signals to specific package pins ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions 4.1 Ball Map View Note: In the following ball map figures the lowercase letter “n”, which normally indicates negation, appears as uppercase “N”. 4.1.1 13x13 mm VF-BGA Ball map Figure 4-1 through Figure 4-1. 13x13 mm VF-BGA Ball Map, Top View (upper left quarter) ...
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... GPIO<44> VCC_CORE GPIO<111> GPIO<41> GPIO<45> USBC_N GPIO<42> GPIO<109> VSS_IO GPIO<39> GPIO<117> VSS_CORE GPIO<115> USBH_P<1> VSS_CORE VSS_CORE VSS_CORE GPIO<68> VSS_CORE Intel® PXA270 Processor Pin Listing and Signal Definitions GPIO<118> VCC_USB VCC_USB USBC_P VCC_USB VCC_USB GPIO<43> GPIO<88> GPIO<116> GPIO<89> USBH_N<1> GPIO<114> UIO ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Figure 4-3. 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) N MD<27> MD<28> MD<12> P VCC_MEM MD<11> MD<26> R MD<24> VSS_MEM MD<25> T MD<23> VCC_CORE MD<8> U MD<7> VCC_MEM VSS_CORE V MD<21> MD<22> MD<6> W MD<20> VCC_MEM VCC_CORE VSS_CORE Y MD< ...
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... GPIO<95> VSS_IO 3> PWR_CAP< GPIO<99> GPIO<93> VCC_BATT GPIO<96> VCC_PLL PXTAL_IN VCC_IO GPIO<98> GPIO<94> VSS_PLL PXTAL_OUT Intel® PXA270 Processor Pin Listing and Signal Definitions GPIO<86> GPIO<87> GPIO<72> GPIO<76> GPIO<75> VCC_LCD GPIO<19> GPIO<74> VCC_CORE TMS TCK TESTCLK GPIO<14> NTRST GPIO<9> TDI VSS_IO VSS GPIO< ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions 4.1.2 23x23 mm PBGA Ball map Figure 4-5. 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter VSS_MEM VSS_MEM B VSS_MEM VCC_MEM C MA[16] MA[17] D MA[14] MA[15] E MA[11] MA[12] F MA[9] VSS_MEM G MA[7] H MA[4] VSS_MEM J MA[3] ...
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... GPIO[25] GPIO[23] GPIO[111] GPIO[92] VSS_IO GPIO[112] GPIO[39] VSS_IO GPIO[110] GPIO[32] GPIO[45] GPIO[117] GPIO[17] GPIO[109] GPIO[35] USBC_P VCC_CORE VSS_CORE VCC_CORE VSS_CORE Intel® PXA270 Processor Pin Listing and Signal Definitions GPIO[41] GPIO[44] VCC_USB VCC_USB B GPIO[34] GPIO[118] GPIO[43] VCC_USB GPIO[89] GPIO[88] D VCC_USB ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Figure 4-7. 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter) M MD[13] MD[11] N MD[28] MD[26] P MD[27] VSS_MEM R MD[10] MD[23] T MD[9] VSS_MEM U MD[22] V MD[20] VSS_MEM W MD[19] MD[18] Y MD[3] MD[17] AA VSS_MEM VCC_MEM AB VSS_MEM VSS_MEM ...
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... The pin usage summary shown in through R15 (VF-BGA through P14 (PBGA), all of which function as VSS_CORE (see the recommendations for connecting the 36 center balls in the Intel® PXA27x Processor Family Design Guide). Each signal’s alternate function inputs are shown in the upper section of each signal row and the outputs are shown in the lower section of each signal row. For example, GPIO< ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 1 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) VCC_MEM D6 A3 MA<25> OCZ C4 C4 MA<24> OCZ D4 E4 MA<23> OCZ C2 D4 MA<22> OCZ D2 E3 MA<21> OCZ E4 F4 MA< ...
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... MD<10> MD<10> — MD<9> MD<9> — MD<8> MD<8> — MD<7> MD<7> — MD<6> MD<6> — Intel® PXA270 Processor Pin Listing and Signal Definitions Third Reset Sleep Alternate State State Function — Refer to Table 4-4 — Refer to Table 4-4 — ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 3 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) ICOC U4 T4 MD<5> Z ICOC Y2 U3 MD<4> Z ICOC Y3 Y1 MD<3> Z ICOC AA3 U4 MD<2> Z ICOC AB1 W3 MD<1> Z ICOC AB4 W4 MD< ...
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... CIF_DD<3> — GPIO<50> nPIOIR BB_OB_DAT<2 Refer to > Table 4-4 CIF_DD<2> — nPIOIW GPIO<51> BB_OB_DAT<3 Refer to > Table 4-4 Intel® PXA270 Processor Pin Listing and Signal Definitions Third Reset Sleep Alternate State State Function — Pu-1 Note[3] Note[1] — — Pu-1 ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 5 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) GPIO<52 ICOC AC14 Y12 > Z GPIO<53 ICOC AB14 AA12 > Z GPIO<54 ICOC AA14 AB13 > Z GPIO<55 ICOC ...
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... L_FCLK_RD — — GPIO<75> — L_LCLK _A0 — — GPIO<76> — L_PCLK_WR — — GPIO<77> — L_BIAS Intel® PXA270 Processor Pin Listing and Signal Definitions Third Reset Sleep Alternate State State Function — Pd-0 Note [3] Note[1] — — Pd-0 Note [3] Note[1] — ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 7 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) GPIO<86 ICOC N22 M20 > Z GPIO<87 ICOC N23 M22 > Z VCC_IO GPIO<11 ICOC C11 A8 > Z GPIO<12 ICOC ...
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... GPIO<43> ICP_TXD BTTXD BTCTS — GPIO<44> — — — — GPIO<45> AC97_SYSCLK BTRTS Intel® PXA270 Processor Pin Listing and Signal Definitions Third Reset Sleep Alternate State State Function — Pd-0 Note [3] Note[1] USB_P3_2 — Pd-0 Note [3] ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 9 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) GPIO<46 ICOC B11 A9 > Z GPIO<47 ICOC A11 C10 > Z GPIO<88 ICOC C23 C22 > Z GPIO<89 ICOC D22 C21 > ...
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... GPIO<113> AC97_RESET_ I2S_SYSCLK CIFDD_<1> — GPIO<114> Note [17] UVS0 DREQ<0> CIF_DD<3> GPIO<115> Note [17] UEN nUVS1 Intel® PXA270 Processor Pin Listing and Signal Definitions Third Reset Sleep Alternate State State Function — Pd-0 Note [3] Note[1] — > — Pd-0 Note [3] Note[1] — ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 11 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) GPIO<11 ICOC C24 E20 6> Z GPIO<11 ICOC D20 C18 7> Z GPIO<11 ICOC A22 B20 8> Z VCC_USB IAOA ...
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... PXTAL_IN PXTAL_IN — PXTAL_OU PXTAL_OUT — T TXTAL_IN TXTAL_IN — TXTAL_OU TXTAL_OUT — T PWR_OUT PWR_OUT — Intel® PXA270 Processor Pin Listing and Signal Definitions Third Reset Sleep Alternate State State Function — Pu-1 Note [8] Input - — Input Note [9] — Low Note [8] — ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 13 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) SUPPLIES VCC_BAT AB20 Y17 PS T A12 B10 VCC_IO PS AD17 W15 VCC_IO PS A16 D14 VCC_IO PS VCC_US B24 A21 ...
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... VCC_CORE — E VCC_COR VCC_CORE — E VCC_COR VCC_CORE — E VCC_COR VCC_CORE — E VCC_COR VCC_CORE — E Intel® PXA270 Processor Pin Listing and Signal Definitions Third Reset Sleep Alternate State State Function — Input Input — Input Input — Input Input — Input Input — ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 15 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) VCC_CO W3 L19 PS RE VCC_CO AD4 VCC_CO VCC_CO AD11 VCC_CO V8 N VCC_CO W11 N VCC_CO R18 N VCC_CO U18 N/A ...
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... VSS_CORE — VSS_CORE VSS_CORE — VSS_CORE VSS_CORE — VSS_CORE VSS_CORE — VSS_CORE VSS_CORE — VSS_CORE VSS_CORE — Intel® PXA270 Processor Pin Listing and Signal Definitions Third Reset Sleep Alternate State State Function — Input Input — Input Input — Input Input — ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions Table 4-1. Pin Usage Summary (Sheet 17 of 17) VF-BGA PBGA Ball# Ball# Name Type (13x13) (23x23) VSS_CO AA15 E16 PS RE VSS_CO M21 E18 PS RE VSS_CO U3 G18 PS RE VSS_CO AA7 J18 PS RE VSS_CO P21 ...
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... Crystal oscillator pins: These pins connect the external crystals to the on-chip oscillators and are not affected by either [2] reset or sleep. For more information, see the “Clocks and Power” chapter in the Intel® PXA27x Processor Family Developer’s Manual. GPIO sleep operation: During the transition into sleep mode, the configuration of these pins is determined by the corresponding GPIO setting ...
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... Memory Controller Reset and Initialization On reset, the SDRAM interface is disabled. Reset values for the boot ROM are determined by BOOT_SEL (see the Intel® PXA27x Processor Family Developers Manual, Memory Controller chapter). Boot ROM is immediately available for reading upon exit from reset, and all memory interface control registers are available for writing ...
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... Name VCC_BATT VCC_IO VCC_USB VCC_LCD VCC_MEM VCC_BB VCC_PLL VCC_SRAM VCC_CORE VCC_USIM VSS VSS_IO VSS_MEM VSS_BB VSS_PLL VSS_CORE Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Pin Listing and Signal Definitions Number of Package Balls Number of Pachage Balls 13x13 mm VF-BGA 23x23 mm PBGA ...
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... Intel® PXA270 Processor Pin Listing and Signal Definitions 4-30 Electrical, Mechanical, and Thermal Specification ...
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... Electrical Specifications 5.1 Absolute Maximum Ratings The absolute maximum ratings (shown in stresses. These limits prevent permanent damage to the Intel® PXA270 processor. Note: Absolute maximum ratings are not operating ranges. Table 5-1. Absolute Maximum Ratings Symbol Description T Storage temperature S Offset voltage between any of the following pins: ...
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... Intel® PXA270 Processor Electrical Specifications Table 5-2 shows each power domains supported voltages (except for VCC_MEM and VCC_CORE). Table 5-3 ranges (VCC_MEM). (VCC_CORE). The operating temperature specification is a function of voltage and frequency. Table 5-2. Voltage, Temperature, and Frequency Electrical Specifications (Sheet ...
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... Table 5-3 shows the supported memory frequency and memory supply voltage operating ranges for the PXA270 processor. Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Electrical Specifications Min Typical Max 2.25 2 ...
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... PXA270 processor. Each frequency range is specified in the following format: (core frequency/internal system bus frequency/memory controller frequency/SDRAM frequency) Note: Refer to the “Clocks and Power” section of the Intel® PXA27x Processor Family Developers Manual for supported frequencies, clock register settings as listed in Table 5-4. Core Voltage and Frequency Electrical Specifications (Sheet ...
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... Core Voltage and Frequency Range 8 (624/208/208/104) VVCCC8 Voltage applied on VCC_CORE fCORE8 Core operating frequency Tpwrramp Ramp Rate †Core operating frequency not offered in PBGA package. Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Electrical Specifications 0.855 0.9 1.705 91 — 104 — ...
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... The external power supplies are used to generate several internal power domains, which are shown in Table 5-5. Refer to the and Power” section of the Intel® PXA27x Processor Family Developers Manual for more information on internal power domains. Table 5-5. Internally Generated Power Domain Descriptions Name ...
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... MHz Idle Power (208 MHz System bus) 312 MHz Idle Power (104 MHz System bus) 208 MHz Idle Power (208 MHz System bus) 104 MHz Idle Power (104 MHz System bus) Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Electrical Specifications Typical Units Conditions VCC_CORE = 1 ...
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... Intel® PXA270 Processor Electrical Specifications Table 5-7. Power-Consumption Specifications (Sheet Parameter Description Low Power modes Power Consumption 1 13 MHz Idle Mode Power (LCD on MHz Idle Mode Power (LCD off) Deep-Sleep mode Sleep mode Standby mode NOTE MHz Idle Mode (CCCR[CPDIS] =1 (CCCR[PPDIS ...
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... Electrical, Mechanical, and Thermal Specification Min VCC - 0.3 VSS Table 5-9 and Table 5-10 kHz crystal pins from an external source: - Minimum — –30 — — ) — ) — O Intel® PXA270 Processor Electrical Specifications Unit Testing Conditions Max s / Notes 2 IOH = - VCC IOH = VSS + 0.3 V ...
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... Intel® PXA270 Processor Electrical Specifications Table 5-9. Typical 32.768-kHz Crystal Requirements (Sheet Parameter Motional capacitance (C Equivalent series resistance (R Insulation resistance at 100 V Aging, at operating temperature per year 5-10 Minimum ) — — S 100 DC — Electrical, Mechanical, and Thermal Specification Typical Maximum Units 2.1 — ...
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... Table 5-11 and Table 5-12 Minimum 12.997 –50 — –50 — ) — ) — S — Intel® PXA270 Processor Electrical Specifications Typical Max Units 1.10 1.21 V 0.00 0.10 V µA — — — — MΩ — ...
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... Intel® PXA270 Processor Electrical Specifications Table 5-12. Typical External 13.000-MHz Oscillator Requirements Symbol Description Amplifier Specifications VIH_X Input high voltage, PXTAL_IN VIL_X Input low voltage, PXTAL_IN IIN_XP Input leakage, PXTAL_IN CIN_XP Input capacitance, PXTAL_IN/PXTAL_OUT tS_XP Stabilization time Board Specifications Parasitic resistance, PXTAL_IN/PXTAL_OUT to ...
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... Rise and Fall time (Tr & Tf) Electrical, Mechanical, and Thermal Specification ) 15nS max with 50pF load Table 5-15 for the 48-MHz output specifications. Refer to Section Intel® PXA270 Processor Electrical Specifications Specifications +/-20pS max 50pf max Specifications 48 MHz +/-200ppm (maximum) 30/70 to 70/30% at VCC ...
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... Intel® PXA270 Processor Electrical Specifications 5-14 Electrical, Mechanical, and Thermal Specification ...
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... Note: The timing diagrams in this chapter show bursts that start at 0 and proceed However, the least significant address (0) is not always received first during a burst transfer, because the Intel® PXA270 processor requests the critical word first during burst accesses. ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-1. AC Test Load 6.2 Reset and Power Manager Timing Specifications The processor asserts the nRESET_OUT pin in one of several different modes: • Power-on reset • Hardware reset • Watchdog reset • GPIO reset • Sleep mode • ...
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... Note: nBATT_FAULT must be high before nRESET is de-asserted. Otherwise, the processor will not begin the power-on sequencing event. nVDD_FAULT is sampled only when the SYS_DEL and PWR_DEL timers have expired. Refer to the Intel® PXA27x Processor Family Developer’s Manual, “Initial Power On” and “Deep-Sleep Exit States” for a state diagram. ...
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... Intel® PXA270 Processor AC Timing Specifications Table 6-2. Power-On Timing Specifications (Sheet 2 of 2)(OSCC[CRI Symbol Description Power-on Ramp Rate for all external high t sysramp -voltage power domains Power-on Ramp Rate for all external low -voltage power domains (including t pwrramp dynamic voltage changes on ...
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... Note: When bit GPROD is set in the Power Manager General Configuration register, nRESET_OUT is not asserted during GPIO reset. For register details, see the “Clocks and Power Manager” chapter in the Intel® PXA27x Processor Family Developer’s Manual. Figure 6-4. GPIO Reset Timing ...
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... Table 6-6 Note: When bit SL_ROD is set in the Power Manager Sleep Configuration register, nRESET_OUT, is not asserted during GPIO reset. See the “Clocks and Power Manager” chapter in the Intel® PXA27x Processor Family Developer’s Manual for register details. 6-6 ...
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... VDD fault) Deep-sleep entry, unless specified. Electrical, Mechanical, and Thermal Specification SLEEP Min 0.56 0. show the required timing parameters for sleep mode. The timing Intel® PXA270 Processor AC Timing Specifications SLEEP (EXIT) NORMAL Texit Tpwrdelay 3 Typical Max Units 1 — ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-6. Deep-Sleep-Mode Timing Intel® PXA27x State: DEEP SLEEP (ENTRY) Wakeup Event Tenable SYS_EN VCC_USB, VCC_IO, VCC_BB, VCC_MEM, VCC_LCD, VCC_USIM PWR_EN Tdentry VCC_CORE, VCC_SRAM, VCC_PLL nVDD_FAULT nRESET_OUT Deep-Sleep Command Table 6-7. Deep-Sleep Mode Timing Specifications ...
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... The delay between the initiation of deep-sleep mode and enabling the GPIO Pu/Pd states, is system dependant because the processor is performing an unpredictable workload and requires an unknown amount of time to complete current processes. Refer to the deep-sleep mode, “Clocks and Power” section of the Intel® PXA27x Processor Family Developers Manual for a description on deep-sleep mode entry sequence. Table 6-8 shows the time period that the GPIO pull-up/pull-downs are enabled ...
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... Intel® PXA270 Processor AC Timing Specifications 6.2.7 Standby-Mode Timing Table 6-9. Standby-Mode Timing Specifications Symbol Description — 13M mode to standby mode entry — Standby mode exit to 13M mode — Run mode to standby mode entry — Standby mode exit to run mode NOTES: 1 ...
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... PMIC Min Max 154 — 62.5 — 154 — 62.5 — 231 — 93.75 — Intel® PXA270 Processor AC Timing Specifications clocked at 40 kHz (160 kHz fast- Table 6-12 shows the timing byte Min Typical Max — 18 — Units Notes ns ...
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... Intel® PXA270 Processor AC Timing Specifications 6.4 Memory and Expansion-Card Timing Specifications Interfaces with the following memories must observe the AC timing requirements given in the following subsections: • Section 6.4.1, “Internal SRAM Read/Write Timing Specifications” • Section 6.4.2, “SDRAM Parameters and Timing Diagrams” ...
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... TBD — — — TBD — VCC_CORE = 1.1 V +/– 10%, with 1.71 V <= VCC_MEM <= 3.63 V Intel® PXA270 Processor AC Timing Specifications VCC_MEM = 4 5 3.3V +/- 10% Units MAX MIN TYP MAX 76.9 9.6 — 76 — 1 SDCLK — ...
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... BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide- by-2 and divide-by-4 register bit MDREFR[KxDB2] clear. 6. Refer to the “Memory Controller” chapter in the Intel® PXA27x Processor Family Developer’s Manual for register configuration. 6-14 ...
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... MD<31:0> write DQM<3:0> RDnWR Electrical, Mechanical, and Thermal Specification tsdRC tsdCL tsdRP tsdCMD nop read pre nop act tsdRAS tsdRCD tsdSDIS tsdIH 0b0000 Intel® PXA270 Processor AC Timing Specifications tsdCMD nop write nop pre nop tsdSDOS tsdSDOH tWR mask data values 6-15 ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-8. SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing SDCLK<1> SDCKE<1> command read(0) pre(1) nSDCS<0> nSDCS<1> nSDRAS nSDCAS col bank MA<24:10> nWE MD<31:0> (read) MD<31:0> (write) DQM<3:0> RDnWR NOTES: 1. MDCNFG[DTC] = 0b00 ( tRP = 2 clk, tRCD = 1 clk), MDCNFG[STACK] = 0b00 2 ...
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... NOTES: 1. MDCNFG[DTC] = 0b01 ( tRP = 2 clks) 2. See the SDRAM timing diagram. Intel® PXA270 Processor AC Timing Specifications nop 6-17 ...
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... ROM reads. Note: Table 6-16 lists programmable register items. See the “Memory Controller” chapter in the Intel® PXA27x Processor Family Developer’s Manual for register configurations for more information on these items. Table 6-16. ROM AC Specification (Sheet ...
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... Numbers shown as integer multiples of the clk_mem period are ideal. Actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). For more information, refer to the “Memory Control” chapter in the Intel® PXA27x Processor Family Developer’s Manual. ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-11. 32-Bit Non-burst ROM, SRAM, or Flash Read Timing CLK_MEM nCS<0> MA<25:2> MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') nADV(nSDCAS) nOE nWE RDnWR MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') nCSx or nSDCSx 6-20 tromAS tromAVDVS tromAVDVF 0b00 0b00 / 0b01 / 0b10 / 0b11 ...
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... RDnWR MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') nCSx or nSDCSx Electrical, Mechanical, and Thermal Specification tAS tromAVDVF tromAVDVS 0b00 0b00 / 0b01 / 0b10 / 0b11 tCES tDOH tDSOH 0b0000 corresponding mask value NOTE: MSC0[RDF0 MSC0[RDN0 MSC0[RRR0 Intel® PXA270 Processor AC Timing Specifications tCEH tromCD 6-21 ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-13. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing CLK_MEM nCS<0> MA<25:4> MA<3> MA<2:1> MA<0>(SA1110x='0') MA<0>(SA1110x='1') nADV(nSDCAS) nOE nWE RDnWR MD<15:0> DQM<1:0>(SA1110x='0') DQM<1:0>(SA1110x='1') nCSx or nSDCSx 6-22 tromAS address tromAVDVS ...
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... SRAM 16-bit burst flash Section 6.4.4.1.2 Table 6-16 for ROM reads also apply to asynchronous flash reads. See 6-12, Figure 6-13, and Figure 6-14 for timings diagrams representative of an Intel® PXA270 Processor AC Timing Specifications tromCD tromCD tromAS tromAS addr addr addr + 1 0 ...
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... Intel® PXA270 Processor AC Timing Specifications 6.4.4.1.2 Synchronous Flash Read Parameters and Timing Diagrams Table 6-17 lists the timing parameters used in Figure 6-16. Table 6-17. Synchronous Flash Read AC Specifications (Sheet Symbols Parameters MIN tffCLK SDCLK0 period 9.6 MA<25:0> setup to tffAS nSDCAS (as ...
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... SDCLK0 period. Electrical, Mechanical, and Thermal Specification TYP MAX MIN TYP MAX — — 0.5 — — — — 1.8 — — Intel® PXA270 Processor AC Timing Specifications MIN TYP MAX Units 0.5 — — ns 1.8 — — ns 6-25 — ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-15. Synchronous Flash Burst-of-Eight Read Timing CLK_MEM SDCLK<0> MA<19:2> MA<1:0>(SA1110x=0) MA<1:0>(SA1110x=1) nCS<0> nADV(nSDCAS) nOE nWE MD<31:0> DQM<3:0>(SA1110x=0) DQM<3:0>(SA1110x=1) 6-26 0b00 0b00/0b01/0b10/0b11 CODE CODE+1 0b0000 corresponding mask value NOTES: 1) SXCNFG[CL] = 0b100 ( frequency code configuration = 4) ...
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... MA<1:0>(SA1110x=0) MA<1:0>(SA1110x=1) nCS<0> nADV(nSDCAS) nOE nWE MD<31:0> DQM<3:0>(SA1110x=0) DQM<3:0>(SA1110x=1) Electrical, Mechanical, and Thermal Specification 0b00 0b00/0b01/0b10/0b11 CODE CODE+1 0b0000 corresponding mask value NOTE: SXCNFG[CL] = 0b100 ( frequency code configuration = 4) SA1110CR[SXSTACK] = 0b01 Intel® PXA270 Processor AC Timing Specifications 6-27 ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-17 indicates which clock data would be latched following the assertion of nSDCAS(ADV), depending on the configuration of the SXCNFG[SXCLx] bit field. The period in the diagram indicated by different frequency configuration codes (Fcodes or FCCs) is equal to the number of SDCLK0 cycles between the READ command and the clock edge on which data is driven onto the bus ...
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... Electrical, Mechanical, and Thermal Specification Figure 6-18 represents waveforms that result when ≥ tVLQV - tVLCH - tCHQV ≥ tCHQV + tffSDIS Table 6- (MHz ≥ n(20 ns ≥ n(20 ns ( (MHz) = 15.15 ns ≥ 15. ≥ 15. Intel® PXA270 Processor AC Timing Specifications for actual synchronous AC 6-29 ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-18. Synchronous Flash Burst Read Example SDCLK<0> tffSDOH nCS<0> nSDCAS (ADV#) tffSDOH MA MD 6.4.4.2 Flash Memory Write Parameters and Timing Diagrams Table 6-18 lists the AC specification for both burst and non-burst flash writes shown in and, for stacked flash Table 6-18 ...
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... Electrical, Mechanical, and Thermal Specification MIN 0 MSCx[RRR]* tflashCD 0b00 tflashASW tflashCEH tflashCES tflashAH tflashWL tflashDH tflashDSWH CMD 0b0000 First Bus Cycle NOTE: MSC0[RDF0 MSC0[RRR0 Intel® PXA270 Processor AC Timing Specifications 1 TYP MAX Units — — clk_mem 15 clk_mem 1 tflashAS data address 0b00 tflashCEH tflashCES tflashAH ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-20. 32-Bit Stacked Flash Write Timing CLK_MEM nWE tflashAS MA<25:2> MA<1:0> tflashASW nCS<0> or nCS<1> nOE RDnWR MD<31:0> DQM<3:0> nADV(nSDCAS) nCSx 6-32 tflashCD command address 0b00 tflashCEH tflashCES tflashAH tflashWL tflashDH tflashDSWH CMD 0b0000 First Bus Cycle ...
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... Burst Flash for ROM reads are also used for SRAM reads. See show the timing for 32-bit and 16-bit SRAM writes. Figure 6-22 and Figure 6-23. Intel® PXA270 Processor AC Timing Specifications tflashCD Figure 6-11). The Figure 6-11 and Table 6-19 ...
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... DQM signals. For SRAM writes, the DQM signals are used as byte enables. Note: Table 6-19 lists programmable register items. See the “Memory Controller”chapter in the Intel® PXA27x Processor Family Developer’s Manual for register configurations for more information on these items. Table 6-19. SRAM Write AC Specification ...
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... Electrical, Mechanical, and Thermal Specification byte addr byte addr tsramASW tsramAH tsramWL tsramWL tsramDH tsramDSWH tsramDOH mask0 mask1 mask2 NOTE: 4-Beat burst, MSC0[RDN0 MSC0[RRR0 Intel® PXA270 Processor AC Timing Specifications 3 byte addr tsramCEHW tsramWL tsramAH tsramWL D3 mask3 tsramCD 6-35 ...
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... Note: Table 6-20 lists programmable register items. For more information on these items, see the “Memory Controller” chapter in the Intel® PXA27x Processor Family Developer’s Manual for register configurations. 6-36 tsramCD ...
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... CLK_MEM cycles), then the data bus could potentially not be driven for 30 CLK_MEM cycles. 6.4.6.1 Variable Latency I/O Read Timing Figure 6-24 shows the timing for 32-bit variable-latency I/O (VLIO) memory reads. lists the timing parameters used in these diagrams. Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor AC Timing Specifications 2 MIN TYP MAX 1 — ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-24. 32-Bit VLIO Read Timing CLK_MEM nCS<0> tvlioAS addr MA<25:2> MA<1:0>(SA1110x='0') MA<1:0>(SA1110x='1') tvlioASRW0 0 Waits nOE nPWE RDnWR RDY RDY_sync MD<31:0> DQM<3:0>(SA1110x='0') DQM<3:0>(SA1110x='1') nCSx or nSDCSx 6.4.6.2 Variable-Latency I/O Write Timing Figure 6-25 shows the timing for 32-bit VLIO memory writes ...
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... Wait 2 Waits tvlioRWD tvlioRWA tvlioRWA tvlioRWD tvlioRDYH tvlioRDYH tvlioDH tvlioDH tvlioDSWH tvlioDSWH tvlioDSWH D1 D2 mask1 mask2 Intel® PXA270 Processor AC Timing Specifications addr + 3 tvlioASRWn tvlioAH tvlioAH 3 Waits tvlioRWA tvlioCEH tvlioRWD tvlioRWA tvlioRDYH tvlioRDYH tvlioDH tvlioDH tvlioDSWH D3 mask3 tvlioCD 6-39 ...
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... The timings are changed by programming the MCx[ASST] respective bit fields. Refer to the PC Card Interface Command Assertion Code table to see the effect of MCx[ASST]. 7. tcdCLPS equals CLK_MEM * x_ASST_WAIT. Refer to the PC Card Interface Command Assertion Code table in the Intel® PXA27x Processor Family Developer’s Manual for the correlation between x_ASST_WAIT and the MCx[ASST] bit field. ...
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... Figure 6-26. Expansion-Card Memory or I/O 16-Bit Access Timing CLK_MEM nPCE[2],nPCE[1] MA[25:0],nPREG,PSKTSEL nPWE,nPOE,nPIOW,nPIOR nIOIS16 MD[15:0] (write) RDnWR nPWAIT MD[15:0] (read) Electrical, Mechanical, and Thermal Specification tcdCLPS tcdPHCH tcdAVCL tcdCMD tcdILCL tcdDVCL Intel® PXA270 Processor AC Timing Specifications Read Data Latch tcdCHAI tcdCHIH tcdCHWDI tcdDVCH tcdCHRDI 6-41 ...
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... Intel® PXA270 Processor AC Timing Specifications Figure 6-27. Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing CLK_MEM MA<25:1>,nPREG,PSKTSEL MA<0> nPCE<2> nPCE<1> nPIOW (or) nPIOR RDnWR nIOIS16 nPWAIT MD<7:0> (read) MD<7:0> (write) 6-42 Read Data Latch tcdAVCL tcdAVCL tcdCMD tcdCHAI tcdILCL tcdPHCH ...
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... These LCD signals can toggle when L_PCLK_WR is not clocking (between frames). At this time, they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK_WR pin. Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor AC Timing Specifications Table 6-22 gives the values for the parameters ...
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... Intel® PXA270 Processor AC Timing Specifications 6.6 SSP Timing Specifications Figure 6-29 describes the SSP timing parameters. The SSP pin timing specifications are referenced to SSPCLK. Table 6-23 Note: In Figure 6-29, read the term “tSFMV” as “TSTXV.” Figure 6-29. SSP Master Mode Timing Definitions ...
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... Clock to Rx Data Capture Rx Data Setup to Capture Parameter Min Max 0.0 33.33 15.0 — 15.0 — — 5.0 — 5.0 Intel® PXA270 Processor AC Timing Specifications Typ Max Units 10.58 ns 10.52 ns Data Capture Data Capture Data Capture Data Capture Typical Max Units 5 ...
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... Intel® PXA270 Processor AC Timing Specifications Table 6-26. Boundary Scan Timing Specifications (Sheet Symbol TBSIS1 Input Setup to TCK TDI, TMS TBSIH1 Input Hold from TCK TDI, TMS TBSIS2 Input Setup to TCK nTRST TBSIH2 Input Hold from TCK nTRST TnTRST Assertion time of nTRST ...
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Glossary 3G: An industry term used to describe the next, still-to-come generation of wireless applications. It represents a move from circuit-switched communications (where a device user has to dial network) to broadband, high-speed, packet-based wireless networks (which ...
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... Intel® PXA270 Processor Glossary BGA: Ball Grid Array BFSK: binary frequency shift keying. A coding scheme for digital data. Bit: A unit of information used by digital computers. Represents the smallest piece of addressable memory within a computer. A bit expresses the choice between two possibilities and is typically represented by a logical one (1) or zero (0). Bit Stuffing: Insertion of a “ ...
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... D-cache: Data cache DECT: the Digital European Cordless Telecommunications standard Default Address: An address defined by the USB Specification and used by a USB device when it is first powered or reset. The default address is 00H. Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Glossary Glossary-3 ...
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... Intel® PXA270 Processor Glossary Default Pipe: The message pipe created by the USB System Software to pass control and status information between the host and a USB device’s endpoint zero. Device: A logical or physical entity that performs a function. The actual entity described depends on the context of the reference. At the lowest level, “ ...
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... For example, a phone call is carried on several different frequencies so that when one frequency is lost another picks up the call without breaking the connection. Fs: See sample rate. FSR: Fault Status Register, part of the ARM* architecture. Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Glossary Glossary-5 ...
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... Intel® PXA270 Processor Glossary Full-duplex: Computer data transmission occurring in both directions simultaneously. Full-speed: USB operation at 12 Mb/s. See also low-speed and high-speed. Function: A USB device that provides a capability to the host, such as an ISDN connection, a digital microphone, or speakers. GMSK: Gaussian Minimum Shift Keying. A modulation scheme used in GSM. ...
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... IMMU: Instruction Memory Management Unit, part of the Intel XScale® core. I-Mode: A Japanese wireless service for transferring packet-based data to handheld devices created by NTT DoCoMo. I-Mode is based on a compact version of HTML and does not currently use WAP. I-cache: Instruction cache IBIS: I/O Buffer Information Specification is a behavioral description of the I/O buffers and package characteristics of a semiconductor device ...
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... Microframe: A 125 microsecond time base established on high-speed buses. MMC: Multimedia Card - small form factor memory and I/O card MMX Technology: The Intel® MMX™ technology comprises a set of instructions that are designed to greatly enhance the performance of advanced media and communications applications. See chapter 10 of the Intel® ...
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... See also stream pipe and message pipe. PLL: See Phase Locked Loop. PM: Phase Modulation. Polling: Asking multiple devices, one at a time, if they have any data to transmit. POR: See Power On Reset. Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Glossary Glossary-9 ...
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... Root Port: The downstream port on a Root Hub. RTC: Real-Time Clock * SA-1110: StrongARM based applications processor for handheld products Intel® StrongARM* SA-1111: Companion chip for the Intel® SA-1110 processor SAD: Sum of absolute differences Glossary-10 Electrical, Mechanical, and Thermal Specification ...
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... Spread Spectrum: An encoding technique patented by actress Hedy Lamarr and composer George Antheil, which broadcasts a signal over a range of frequencies. SRAM: Static Random Access Memory. SRC: See Sample Rate Conversion. SSE: Streaming SIMD Extensions Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Glossary Glossary-11 ...
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... Intel® PXA270 Processor Glossary SSE2: Streaming SIMD Extensions 2: for Intel Architecture machines, 144 new instructions, a 128-bit SIMD integer arithmetic and 128-bit SIMD double precision floating point instructions, enabling enhanced multimedia experiences. SSP: Synchronous Serial Port SSTL: Stub series terminated logic Stage: One part of the sequence composing a control transfer ...
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... Internet content, check voice mail and e-mail, receive text of faxes and conduct transactions. WAP works with multiple standards, including CDMA and GSM. Not all mobile devices support WAP. Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Glossary Glossary-13 ...
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... Intel® PXA270 Processor Glossary W-CDMA: Wideband CDMA, a third generation wireless technology under development that allows for high-speed, high-quality data transmission. Derived from CDMA, W-CDMA digitizes and transmits wireless data over a broad range of frequencies. It requires more bandwidth than CDMA, but offers faster transmission because it optimizes the use of multiple wireless signals, instead of one, as does CDMA ...
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... Expansion-Card Interface Parameters and Timing Diagrams 40 F Flash Memory Read Parameters and Timing Diagrams ..23 Flash Memory Write Parameters and Timing Diagrams .30 Functional Overview ..........................................................1 Intel® PXA270 Processor G GPIO states in Deep-Sleep mode ...................................... 9 I Internal SRAM Read/Write Timing Specifications ......... 12 Introduction ....................................................................... 1 About This Document ............................................... 1 Applicable Documents ...
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... Index-2 Intel® PXA270 Processor ...