ATF16V8CZ-15XU Atmel, ATF16V8CZ-15XU Datasheet

IC PLD 15NS 20TSSOP

ATF16V8CZ-15XU

Manufacturer Part Number
ATF16V8CZ-15XU
Description
IC PLD 15NS 20TSSOP
Manufacturer
Atmel
Datasheet

Specifications of ATF16V8CZ-15XU

Programmable Type
EE PLD
Number Of Macrocells
8
Voltage - Input
5V
Speed
15ns
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Family Name
ATF16V8CZ
Process Technology
EECMOS
# Macrocells
8
# I/os (max)
8
Frequency (max)
62MHz
Propagation Delay Time
15ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
105mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF16V8CZ-15XU
Manufacturer:
ATMEL
Quantity:
6
Features
1. Description
The ATF16V8CZ is a high-performance EECMOS programmable logic device that uti-
lizes Atmel’s proven electrically-erasable Flash memory technology. Speeds down to
12 ns and a 5 µA (Typ) edge-sensing power-down mode are offered. All speed ranges
are specified over the full 5V ±10% range for industrial temperature ranges; 5V ±5%
for commercial range 5-volt devices.
The ATF16V8CZ incorporates a superset of the generic architectures, which allows
direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight out-
puts are each allocated eight product terms. Three different modes of operation,
configured automatically with software, allow highly complex logic functions to be
realized.
The ATF16V8CZ can significantly reduce total system power, thereby enhancing sys-
tem reliability and reducing power supply costs. When all the inputs and internal
nodes are not switching, supply current drops to less than 5 µA typically. This auto-
matic power-down feature (or sleep mode) allows for power savings in slow clock
systems and asynchronous applications. Also, the pin-keeper circuits eliminate the
need for internal pull-up resistors along with their attendant power consumption.
Industry-standard Architecture
High-speed Electrically-erasable Programmable Logic Devices
Low-power - 5 µA (Typ) Standby Current
CMOS and TTL Compatible Inputs and Outputs
Advanced Flash Technology
High-reliability CMOS Process
Commercial and Industrial Temperature Ranges
Dual-in-line and Surface Mount Packages in Standard Pinouts
PCI-compliant
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
– Emulates Many 20-pin PALs
– Low-cost Easy-to-use Software Tools
– 12 ns Maximum Pin-to-pin Delay
– Input and I/O Pin Keeper Circuits
– Reprogrammable
– 100% Tested
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
High-
performance
EE PLD
ATF16V8CZ
0453H–PLD–7/05

Related parts for ATF16V8CZ-15XU

ATF16V8CZ-15XU Summary of contents

Page 1

... The ATF16V8CZ can significantly reduce total system power, thereby enhancing sys- tem reliability and reducing power supply costs. When all the inputs and internal nodes are not switching, supply current drops to less than 5 µA typically. This auto- matic power-down feature (or sleep mode) allows for power savings in slow clock systems and asynchronous applications ...

Page 2

... Figure 1-1. Block Diagram 2. Pin Configuration and Pinouts Table 2-1. Pin Name CLK I I/O OE VCC Figure 2-1. Figure 2-2. ATF16V8CZ 2 Pinouts - All Pinouts Top View Function Clock Logic Inputs Bi-directional Buffers Output Enable +5V Supply TSSOP I/CLK GND 10 DIP/SOIC I/CLK GND 10 20 ...

Page 3

... OUT 25°C CC Min < V < Max Min, All Outputs - ATF16V8CZ 18 I/O 17 I/O 16 I/O 15 I/O 14 I/O Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...

Page 4

... DC Characteristics Symbol Parameter V Output High Voltage OH I Output Low Current OL I Output High Current OH Note: 1. All I parameters measured with outputs open. Data is based on Atmel test patterns. Reading may vary with pattern. CC ATF16V8CZ 4 Condition V = Min -3 Com Min CC Ind Min Com., Ind. ...

Page 5

... S f Internal Feedback 1/( MAX S No Feedback 1/( Input to Output Enable – Product Term EA t Input to Output Disable – Product Term pin to Output Enable PZX t OE pin to Output Disable PXZ 0453H–PLD–7/05 Min 1.5 ATF16V8CZ -12 -15 Max Min 1.5 Max Units MHz ...

Page 6

... Pin Capacitance Table 4- OUT Note: ATF16V8CZ 6 Similar devices are tested with slightly different loads. These load differences may affect output signals' delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible devices. Pin Capacitance ( MHz Typ Max ...

Page 7

... Once downloaded, the JEDEC file preload sequence will be done automati- cally by approved programmers. 5. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF16V8CZ fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. ...

Page 8

... The ATF16V8CZ contains internal input and I/O pin-keeper circuits. These circuits allow each ATF16V8CZ pin to hold its previous value even when it is not being driven by an external source or by the device’s output buffer. This helps insure that all logic array inputs are at known, valid logic levels ...

Page 9

... These architectural subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF16V8CZ can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. ...

Page 10

... ATF16V8CZ Registered Mode PAL Device Emulation/PAL Replacement. The registered mode is used if one or more regis- ters are required. Each macrocell can be configured as either a registered or combinatorial output or I/ input ...

Page 11

... The development software configures all the architecture control bits and checks for proper pin usage automatically. Combinatorial Configuration for Registered Mode 1. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the architecture control bits and checks for proper pin usage automatically. ATF16V8CZ (1)(2) (1)(2) 11 ...

Page 12

... Figure 8-3. Registered Mode Logic Diagram ATF16V8CZ 12 0453H–PLD–7/05 ...

Page 13

... Figure 8-4. 9. ATF16V8CZ Simple Mode PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinato- rial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array ...

Page 14

... Figure 9-1. ATF16V8CZ 14 Simple Mode Option 0 1 0453H–PLD–7/05 ...

Page 15

... Figure 9-2. Complex Mode Logic Diagram 0453H–PLD–7/05 ATF16V8CZ 15 ...

Page 16

... Figure 9-3. Simple Mode Logic Diagram ATF16V8CZ 16 0453H–PLD–7/05 ...

Page 17

... Test Characterization Data 0453H–PLD–7/05 ATF16V8CZ 17 ...

Page 18

... ATF16V8CZ 18 0453H–PLD–7/05 ...

Page 19

... ATF16V8CZ 19 ...

Page 20

... ATF16V8CZ-15JC 20J ATF16V8CZ-15PC 20P3 20S ATF16V8CZ-15SC 20X ATF16V8CZ-15XC ATF16V8CZ-15JI 20J ATF16V8CZ-15PI 20P3 20S ATF16V8CZ-15SI 20X ATF16V8CZ-15XI Ordering Code Package ATF16V8CZ-15JU 20J ATF16V8CZ-15PU 20P3 ATF16V8CZ-15SU 20S ATF16V8CZ-15XU 20X Package Type Operation Range Commercial ( Commercial ( Industrial (- Operation Range Industrial (- 0453H–PLD–7/05 ...

Page 21

... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 0453H–PLD–7/05 PIN NO. 1 1.14(0.045) X 45˚ IDENTIFIER TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) ATF16V8CZ 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 4.191 – ...

Page 22

... A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R ATF16V8CZ 22 D PIN TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual ...

Page 23

... TITLE 20S, 20-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) ATF16V8CZ 7.60 (0.2992) 10.65 (0.419) 10.00 (0.394) 7.40 (0.2914) 2.65 (0.1043) 2.35 (0.0926) 0.32 (0.0125) 0.23 (0.0091) DRAWING NO ...

Page 24

... TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC 0.65 (.0256) BSC 0º ~ 8º 2325 Orchard Parkway San Jose, CA 95131 R ATF16V8CZ 24 PIN 1 4.50 (0.177) 4.30 (0.169) 6.60 (.260) 6.40 (.252) 0.15 (0.006) 0.30 (0.012) 0.05 (0.002) ...

Page 25

... Revision History 12.1 0453H 1. Green Package options added in 2005. 0453H–PLD–7/05 ATF16V8CZ 25 ...

Page 26

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

Related keywords