PALCE16V8-15JC Cypress Semiconductor Corp, PALCE16V8-15JC Datasheet - Page 6

• Manufacturer Part Number: PALCE16V8-15JC
• Description: IC SPLD 8 MACROCELL 15NS 20-PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of PALCE16V8-15JC

• Programmable Type: PAL FLASH
• Number Of Macrocells: 8
• Voltage - Input: 5V
• Speed: 15ns
• Mounting Type: Surface Mount
• Package / Case: 20-PLCC
• Family Name: Pal®
• Process Technology: EECMOS
• # Macrocells: 8
• # I/os (max): 8
• Frequency (max): 62.5MHz
• Propagation Delay Time: 15ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Supply Current: 90mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1277

Commercial and Industrial Switching Characteristic
Document #: 38-03025 Rev. **
Parameter
t
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
Shaded area contains preliminary information.
Notes:
10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
PD
PZX
PXZ
EA
ER
CO
S
H
P
WH
WL
MAX1
MAX2
MAX3
CF
PR
8.
9.
Min. times are tested initially and after any design or process changes that may affect these parameters.
This specification is guaranteed for all device outputs changing state in a given access cycle.
HIGH level has fallen to 0.5 volts below V
Input to Output
Propagation
Delay
OE to Output
Enable
OE to Output
Disable
Input to Output
Enable Delay
Input to Output
Disable Delay
Clock to Output
Delay
Input or Feedback
Set-Up Time
Input Hold Time
External Clock
Period (t
Clock Width HIGH
Clock Width LOW
External Maximum
Frequency
(1/(t
Data Path Maximum Fre-
quency (1/(t
Internal Feedback
Maximum Frequency
(1/(t
Register Clock to
Feedback Input
Power-Up Reset Time
CO
CF
[8, 9]
[8,9]
Description
+ t
+ t
CO
S
S
))
))
[7, 13]
+ t
[7, 11]
WH
[7]
[7, 10]
S
)
+ t
[7, 14]
WL
[7]
[7]
))
OH
[7, 12]
[7]
min. or a previous LOW level has risen to 0.5 volts above V
Min.
143
166
166
1
1
1
1
1
1
3
0
7
3
3
1
16V8-5
MAX
Max.
internal (1/f
5
6
5
6
5
4
3
Min.
MAX3
100
125
125
10
3
2
5
0
4
4
1
16V8-7
) as measured (see Note 7 above) minus t
Max.
7.5
6
6
9
9
5
3
s
[ 2 ]
Min.
14.5
7.5
69
83
74
3
2
0
6
6
1
16V8-10
OL
Max.
max.
10
10
10
10
10
7
6
Min.
45.5
62.5
12
22
50
3
2
0
8
8
1
16V8-15
S
.
Max.
15
15
15
15
15
10
8
Min.
41.6
15
27
12
12
37
40
3
2
0
1
16V8-25
PALCE16V8
Max.
25
20
20
25
25
12
10
Page 6 of 13
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s