CS4265-CNZ Cirrus Logic Inc, CS4265-CNZ Datasheet
CS4265-CNZ
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CS4265-CNZ Summary of contents
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... Filter Anti-Alias Filter Multibit Low-Latency Oversampling Anti-Alias Filter Filter Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS4265 ± Gain, 0.5 dB Step Size Zero Crossing, Click-Free Transitions +32 dB Gain Stage Low-Noise Bias Supply Left-Justified up to 24-bit I² 24-bit 3 Switched Capacitor ...
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... Integrated level translators allow easy interfacing be- tween the CS4265 and other devices operating over a wide range of logic levels. The CS4265 is available in a 32-pin QFN package for both Commercial (-10° to +70° C) and Automotive (-40° to +105° C) grade. The CDB4265 is also available for device evaluation and implementation suggestions ...
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... REGISTER DESCRIPTION .................................................................................................................. 35 6.1 Chip ID - Register 01h .................................................................................................................... 35 6.2 Power Control - Address 02h ......................................................................................................... 35 6.2.1 Freeze (Bit 7) ......................................................................................................................... 35 6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 35 6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 35 6.2.4 Power-Down DAC (Bit 1) ....................................................................................................... 36 6.2.5 Power-Down Device (Bit 0) ................................................................................................... 36 6.3 DAC Control - Address 03h ............................................................................................................ 36 DS657F2 .......................................................................................................................... 7 CS4265 3 ...
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... Mono Mode Channel Selection (Bit 0) ................................................................................. 45 7. PARAMETER DEFINITIONS ................................................................................................................ 46 8. DAC FILTER PLOTS 9. ADC FILTER PLOTS 10. EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS ............................................................... 51 10.1 IEC60958-3 Transmitter External Components ............................................................................ 51 10.2 Isolating Transformer Requirements ............................................................................................ 51 11. CHANNEL STATUS BUFFER MANAGEMENT ................................................................................ 52 11.1 IEC60958-3 Channel Status (C) Bit Management ........................................................................ 52 4 .................................................................................................................... 47 ......................................................................................................................... 49 CS4265 DS657F2 ...
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... Figure 34.ADC Double-Speed Stopband Rejection .................................................................................. 49 Figure 35.ADC Double-Speed Stopband Rejection .................................................................................. 49 Figure 36.ADC Double-Speed Transition Band (Detail) ............................................................................ 50 Figure 37.ADC Double-Speed Passband Ripple ...................................................................................... 50 Figure 38.ADC Quad-Speed Stopband Rejection ..................................................................................... 50 Figure 39.ADC Quad-Speed Stopband Rejection ..................................................................................... 50 Figure 40.ADC Quad-Speed Transition Band (Detail) .............................................................................. 50 Figure 41.ADC Quad-Speed Passband Ripple ......................................................................................... 50 DS657F2 ........................................................................................................ 56 CS4265 5 ...
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... Table 11. DAC SDIN Source Selection ..................................................................................................... 39 Table 12. Example Gain and Attenuation Settings ................................................................................... 39 Table 13. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 40 Table 14. Analog Input Selection .............................................................................................................. 40 Table 15. Digital Volume Control Example Settings ................................................................................. 41 Table 16. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 42 Table 17. Transmitter Digital Interface Formats ........................................................................................ 44 6 CS4265 DS657F2 ...
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... MICIN2 15 tion table. 16 Microphone Bias (Output) - Low noise bias supply for external microphone. Electrical characteristics MICBIAS are specified in the DC Electrical Characteristics table. DS657F2 Thermal Pad Top-Down (Through Package) View 32-Pin QFN Package CS4265 26 25 SDIN2 24 TXSDIN 23 VLS 22 MUTEC 21 AOUTB 20 AOUTA 19 AGND ...
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... Digital Ground (Input) - Ground reference for the internal digital section Digital Power (Input) - Positive power for the internal digital section. TXOUT 32 Transmitter Line Driver Output (Output) - IEC60958-3 driver output. Thermal Pad - Thermal Pad - Thermal relief pad for optimized heat dissipation. 8 CS4265 DS657F2 ...
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... Analog VA Digital VD Logic - Serial Port VLS Logic - Control Port VLC (Note AGND-0.3 INA V Logic - Serial Port IND-S Logic - Control Port V IND stg CS4265 Nom Max Units 5.0 5.25 V 3.3 (Note 1) V 3.3 5.25 V 3.3 5.25 V °C - +70 - +105 °C Min Max Units -0 ...
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... THD -90 - -70 - -30 (1 kHz) - 100 - 0.1 - 100 0.60*VA 0.65*VA 0.70*VA 0.60*VA 0.65*VA 0.70*VA (Note OUT (Note (Note 150 OUT CS4265 = 3 kΩ (see L L Figure 9 on Automotive Grade Max Min Typ Max - 96 104 - - 93 101 - - -84 - - -41 - -87 - - ...
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... L Symbol to -0.1 dB corner corner -0.175 0.5465 (Note 8) tgd Fs = 44.1 kHz to -0.1 dB corner corner 0.5770 (Note 8) tgd to -0.1 dB corner corner (Note 8) tgd CS4265 affects the dominant pole of the L Min Typ Max Unit Single-Speed Mode 0.4992 - +0. ...
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... AOUTx R L AGND Figure 1. DAC Output Test Load 12 125 100 V 75 out 2 Figure 2. Maximum DAC Loading CS4265 Safe Operating Region Resistive Load -- R (k Ω DS657F2 ...
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... Figure 9 on page 23. Line-Level Inputs Commercial Grade Symbol Min Typ 98 104 95 101 - (Note 12 -95 - - -92 THD -92 - -75 - - 101 (Note 12 -92 - - THD -89 - - -81 CS4265 = -10° to +70° C for Commercial or -40° to Automotive Grade Max Min Typ Max - 96 104 - - 93 101 - - - -89 - - -92 - -86 - - 101 - - ...
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... Symbol Min Typ - ± - 100 0.51*VA 0.57*VA 0.63*VA 0.51*VA 0.57*VA 0.63*VA (Note 11) 6.12 6 Line-Level and Microphone-Level Inputs Commercial Grade Symbol Min Typ - 0 CS4265 Automotive Grade Max Min Typ Max Unit - - 90 - ± 10 ± ± 100 - ppm/°C 7.48 5.44 6.8 8.16 ...
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... Valid for Double- and Quad-Speed Modes only. 14. Valid when the microphone-level inputs are selected. DS657F2 Microphone-Level Inputs Commercial Grade Symbol Min Typ -80 - -60 THD -80 - -60 THD ± ± - 300 0.013*VA 0.017*VA 0.021*VA 0.013*VA 0.017*VA 0.021* CS4265 Automotive Grade Max Min Typ Max - -74 - - -74 - -80 - -60 ...
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... Response is clock-dependent and will scale with Fs. Note that the response plots normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 16 Symbol Min Typ 0.5688 - 12/ 0.5604 - 9/ 0.5000 - 5/ (Note 16) 20 (Note 16 /Fs (Figures 30 CS4265 Max Unit 0.4896 Fs 0.035 0.4896 Fs 0.025 0.2604 Fs 0.025 Deg 41) are DS657F2 ...
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... Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors. DS657F2 Symbol 3 VD, VLS, VLC = VD, VLS, VLC = 3 VLS, VLC, VD (Note 19) PSRR VQ (Note 20 FILT+ MICBIAS I MB CS4265 Min Typ Max - 0. 0. 400 485 - 198 241 - 4 0 ...
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... Control Port V 0.8xVLC IH Serial Port V 0.7xVLS IH Control Port V 0.7xVLC IH Serial Port Control Port Serial Port V VLS-1.0 OH Control Port V VLC-1.0 OH MUTEC V VA-1.0 OH TXOUT V VD-1.0 OH Serial Port Control Port MUTEC TXOUT (Note 22 CS4265 Typ Max Units - - 0.2xVLS V - 0.2xVLC 0.4 V μA - ± DS657F2 ...
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... L Symbol Single-Speed Mode Fs Double-Speed Mode Fs Quad-Speed Mode Fs f mclk t clkhl t slr t sdo t sdis t sdih Single-Speed Mode t sclkw Double-Speed Mode t sclkw Quad-Speed Mode t sclkw t sclkh t sclkl t slr t sdo t sdis t sdih page 20. CS4265 Min Typ Max 100 100 - 200 1.024 - 51.200 - ...
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... LRCK O utput SCLK O utput SDO UT SDIN Figure 3. Master Mode Serial Audio Port Timing LRCK Input SCLK Input SDOUT SDIN 20 t slr t sdo t sdis t t sclkh slr t sclkw t sdo t sdis Figure 4. Slave Mode Serial Audio Port Timing CS4265 t sdih t sclkl t sdih DS657F2 ...
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... MSB - LRCK Channel A - Left SCLK SDATA LSB MSB - DS657F2 + LSB MSB + LSB MSB Figure 6. Format 1, I² 24-Bit Data - LSB Figure 7. Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. CS4265 Channel B - Right - LSB Channel B - Right + LSB Channel B - Right MSB - LSB 21 ...
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... Figure 8. Control Port Timing - I²C Format CS4265 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 fd 4.7 - 300 1000 , of SCL ate d Sta rt ...
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... TXSDIN Note 2 : CS4265 For best response to Fs/2 : MCLK SCLK This circuitry is intended for applications where the CS4265 connects directly to an unbalanced output of the design . For internal LRCK routing applications please see the DAC Analog Output Characteristics section for loading limitations. AIN1A TXOUT 10 µ ...
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... The desired register settings can be loaded while the PDN bit remains set. 4. Clear the PDN bit to initiate the power-up sequence. 4.2 System Clocking The CS4265 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed modes as shown in 4.2.1 Master Clock MCLK/LRCK must maintain an integer ratio as shown in frequency at which audio samples for each channel are clocked into or out of the device ...
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... High-Pass Filter and DC Offset Calibration When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven into the A/D converter. The CS4265 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul- tichannel system ...
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... Any unused analog input pairs should be left unconnected. 4.5.1 Pseudo-Differential Input The CS4265 implements a pseudo-differential input stage. The SGND input is intended to be used as a pseudo-differential reference signal. This feature allows for common mode noise rejection with single- ended signals. ...
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... The recommended external analog circuitry is shown in the Typical Connection Diagram. The CS4265 DAC does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response is dependent on the external analog circuitry. 4.7 ...
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... DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See Selection - Address 06h” section on page When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4265. Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the format selected by the DAC_DIF[1:0] bits ...
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... The transmitter is clocked from the clock input pin MCLK. The channel status (C) bits in the transmitted data stream are taken from storage areas within the CS4265. The user can manually access the internal storage of the CS4265 to configure the transmitted channel sta- tus data. The “ ...
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... MAP will be output. Following each data byte, the memory address pointer will automatically increment to facilitate block reads and writes of successive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4265 after each input byte is read, and is input to the CS4265 from the microcontroller after each transmitted byte. ...
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... Send stop condition. 4.14 Status Reporting The CS4265 has comprehensive status reporting capabilities. Many conditions can be reported in the status register, as listed in the status register descriptions. See may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive ...
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... CS4265s in the system. If only one master clock source is needed, one solution is to place one CS4265 in Master Mode, and slave all of the other CS4265s to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS4265 reset with the inactive edge of master clock ...
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... Gain3 PGASoft PGAZero Vol6 Vol5 Vol4 Vol3 Vol6 Vol5 Vol4 Vol3 Reserved EFTC ClkErr EFTCM ClkErrM EFTC1 ClkErr1 EFTC0 ClkErr0 CS4265 REV2 REV1 PDN_ADC PDN_DAC MuteDAC DeEmph Reserved MuteADC HPFFreeze Reserved Reserved Reserved Reserved LOOP Reserved Gain2 Gain1 Gain2 Gain1 Reserved ...
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... Addr Function 7 11h Transmitter Reserved Control 1 0 12h Transmitter Tx_DIF1 Tx_DIF0 Control 2 0 13h - C-Data Buffer - 2Ah EFTCI CAM Reserved Reserved TxOff TxMute CS4265 Reserved Reserved MMT MMTCS Reserved 0 MMTLR 0 - DS657F2 ...
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... The ADC pair will remain in a reset state whenever this bit is set. DS657F2 PART0 REV3 Table 4 REV[2:0] Revision 001 010 B, C0 011 Table 4. Device Revision Reserved PDN_MIC Name Register 03h 04h 07h 08h 0Ah 0Bh 0Eh Table 5. Freeze-able Bits CS4265 2 1 REV2 REV1 below PDN_ADC PDN_DAC Bit( 5:0 5:0 7:0 7 REV0 0 PDN 35 ...
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... The muting function is effected, similar to attenuation changes, by the DACSoft and DACZero bits in the DAC Control 2 register DAC_DIF0 Reserved Table 6 and Figures Description Left Justified 24-bit data (default) I² 24-bit data Right-Justified, 16-bit Data Right-Justified, 24-bit Data Table 6. DAC Digital Interface Formats CS4265 MuteDAC DeEmph Reserved 5-7. Format Figure ...
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... Reserved Mode Single-Speed Mode kHz sample rates Double-Speed Mode 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Reserved Table 8. Functional Mode Selection Table 9 and may be seen in CS4265 Figure 17, may be implemented for a sample Table 7. NOTE: De-emphasis is available µs Frequency 2 1 ...
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... Reserved Reserved 38 Description I² 24-bit data Table 9. ADC Digital Interface Formats “High-Pass Filter and DC Offset Calibration” MCLK Reserved Freq0 Table 10 MCLK Freq2 MCLK Freq1 Table 10. MCLK Frequency CS4265 Format Figure Reserved Reserved Reserved for the appropriate settings. MCLK Freq0 DS657F2 ...
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... Reserved Reserved SDINSel Setting DAC Data Source 0 SDIN1 1 SDIN2 Table 11. DAC SDIN Source Selection 28 Gain4 Gain3 Gain4 Gain3 Gain[5:0] Setting 101000 -12 dB 000000 0 dB 011000 +12 dB CS4265 Reserved LOOP Reserved Table 11 Gain2 Gain1 Gain0 Gain2 Gain1 Gain0 Table 12 for ex- 39 ...
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... DAC Channel B Volume Control - Address PGASoft PGAZero 13. Table 13. 0 Changes to affect immediately 1 Zero Cross enabled 0 Soft Ramp enabled 1 Soft Ramp and Zero Cross enabled (default) (Bit 0) PGA/ADC Input 0 Microphone-Level Input 1 Line-Level Input Table 14. Analog Input Selection 0Bh. CS4265 Reserved Reserved Select Mode Table 14. DS657F2 ...
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... DS657F2 Vol4 Vol3 Section 6.12.1). Binary Code Volume Setting 00000000 0 dB 00000001 -0.5 dB 00101000 -20 dB 00101001 -20.5 dB 11111110 -127 dB 11111111 -127 Reserved Reserved 16. CS4265 Vol2 Vol1 Vol0 Reserved Reserved Reserved 41 ...
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... ADC Underflow (Bit 0) Function: Indicates the occurrence of an ADC underflow condition. 42 Table 16. DACZeroCross 0 Changes to affect immediately 1 Zero Cross enabled 0 Soft Ramp enabled 1 Soft Ramp and Zero Cross enabled (default EFTC ClkErr CS4265 Mode 2 1 Reserved ADCOvfl ADCUndrfl “Channel Status Buffer Management” DS657F2 ...
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... Two-byte control port access mode. See agement” on page 52. DS657F2 EFTCM ClkErrM EFTC1 ClkErr1 EFTC0 ClkErr0 Reserved Reserved CS4265 2 1 Reserved ADCOvflM ADCUndrflM “Status - Address 0Dh” Reserved ADCOvfl1 ADCUndrfl1 Reserved ADCOvfl0 ADCUndrfl0 2 1 Reserved Reserved Reserved “IEC60958-3 Channel Status (C) Bit Man- ...
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... TxMute V Table 17 Description Left Justified 24-bit data (default) I² 24-bit data Right-Justified, 16-bit Data Right-Justified, 24-bit Data Table 17. Transmitter Digital Interface Formats 52) and the CS data defined by the MMTCS bit (see Section 6.18.6). CS4265 MMT MMTCS MMTLR and Figures 5-7. Format Figure ...
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... Mono Mode Channel Selection (Bit 0) Function: When this bit is cleared, channel A input data will be transmitted in both channel A and B subframes in mono mode. When this bit is set, channel B input data will be transmitted in both channel A and B sub- frames in Mono Mode. DS657F2 CS4265 45 ...
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... Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. 46 CS4265 DS657F2 ...
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... Figure 22. DAC Double-Speed Stopband Rejection DS657F2 Figure 19. DAC Single-Speed Transition Band 0.05 0 -0.05 -0. 1 -0.15 -0. 2 -0.25 0 0.05 0.1 0.52 0.53 0.54 0.5 5 Figure 21. DAC Single-Speed Passband Ripple Figure 23. DAC Double-Speed Transition Band CS4265 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs) 47 ...
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... Figure 27. DAC Quad-Speed Transition Band 0 - -1. 5 0.6 0.65 0.7 0 0.05 Figure 29. DAC Quad-Speed Passband Ripple CS4265 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (normalized to Fs) 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Frequency(normalized to Fs) 0.1 ...
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... Figure 35. ADC Double-Speed Stopband Rejection CS4265 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (norm alized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (norm alized to Fs) 0 ...
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... Figure 41. ADC Quad-Speed Passband Ripple CS4265 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Frequency (norm alized to Fs) ...
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... Please refer to Cirrus application note AN134: AES and SPDIF Recommended Transformers for resources on transformer selection. DS657F2 provides the proper output impedance and drive level using standard 1% re- 374-R TXP TXO UT CS4265 90.9 Ω TXOUT CS4265 Figure 43. TTL/CMOS Output Circuit CS4265 Figure 43. This circuit may be used hon o TTL or CMOS Gate 51 ...
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... IEC60958-3 Channel Status (C) Bit Management The CS4265 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits). The user may read from, or write to, these RAM buffers through the control port. The CS4265 manages the flow of channel status data at the block level, meaning that entire blocks of chan- nel status information are buffered at the input, synchronized to the output time base, and then transmitted ...
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... CS4265, through the control port. The user can modify the data to be transmitted by writing to the E buffer. The E buffer is only accessible when an MCLK signal is applied to the CS4265 and the device is out of the power-down state (the PDN bit in register 02h is cleared). If either of these conditions is not met, the values stored in the E buffer will not change when written via the control port ...
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... In these situations, Two-Byte Mode should be used to access the E buffer. In this mode, a read will cause the CS4265 to output two bytes from its control port. The first byte out rep- resents the A channel status data, and the second byte represents the B channel status data. Writing is similar, in that two bytes must now be input to the CS4265's control port. The A channel status data is first ...
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... JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol 2 Layer Board θ Layer Board CS4265 b e Pin #1 Corner D2 Bottom View MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.23 0.28 5.00 BSC 3.30 3.35 5.00 BSC 3 ...
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... CS4265 Container Order # Tube CS4265-CNZ -10° to +70° C Tape & Reel CS4265-CNZR Tube CS4265-DNZ Tape & Reel CS4265-DNZR - - CDB4265 I²C Control Port Description and Timing description on page 35. table on page ADC Analog Characteristics table on page 19 ...