CS42L55-CNZ Cirrus Logic Inc, CS42L55-CNZ Datasheet
CS42L55-CNZ
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CS42L55-CNZ Summary of contents
Page 1
... Level Shifter I²S Serial Audio Control Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS42L55 Noise Gate for Noise Suppression Programmable Threshold & Attack/Release Rates Stereo Anlg. Passthrough: 3.3 mW @1.8 V Stereo Rec. and Playback: 8.3 mW @1.8 V (SYSTEM FEATURES continued on +1. +2.71 V ...
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... These features make the CS42L55 the ideal solution for portable applications that require extremely low power consumption in a minimal amount of space. The CS42L55 is available in a 36-pin QFN package for the Commercial (-40°C to +85°C) grade. The CDB42L55 Customer Demonstration board is also available for device evaluation and implementation sug- gestions ...
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... Recommended DAC Line Power-Up Sequence (Playback) .......................................... 35 4.11.1 Recommended Power-Down Sequence ............................................................................. 36 4.12 Recommended PGA Line Power-Up Sequence (Analog Passthrough) ......................... 36 4.12.1 Recommended Power-Down Sequence ............................................................................. 36 4.13 Required Initialization Settings ..................................................................................................... 37 4.14 Control Port Operation .................................................................................................................. 38 4.14.1 I²C Control ........................................................................................................................... 38 4.14.2 Memory Address Pointer (MAP) .......................................................................................... 39 4.14.2.1 Map Increment (INCR) ............................................................................................. 39 DS773F1 CS42L55 3 ...
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... Boostx ................................................................................................................................. 49 6.11.2 PGA x Input Select .............................................................................................................. 49 6.11.3 PGAx Volume ...................................................................................................................... 49 6.12 ADCx Attenuator Control: ADCAATT (Address 0Dh) & ADCBATT (Address 0Eh) ....................................................................... 50 6.12.1 ADCx Volume ...................................................................................................................... 50 6.13 Playback Control 1 (Address 0Fh) ................................................................................................ 50 6.13.1 Power Down DSP ................................................................................................................ 50 6.13.2 HP/Line De-Emphasis ......................................................................................................... 50 6.13.3 Playback Channels B=A ...................................................................................................... 50 4 CS42L55 DS773F1 ...
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... Peak Detect and Limiter ...................................................................................................... 61 6.27.2 Peak Signal Limit All Channels ........................................................................................... 61 6.27.3 Limiter Release Rate ........................................................................................................... 62 6.28 Limiter Attack Rate (Address 23h) ................................................................................................ 62 6.28.1 Limiter Attack Rate .............................................................................................................. 62 6.29 ALC Enable & Attack Rate (Address 24h) .................................................................................... 62 6.29.1 ALCx .................................................................................................................................... 62 6.29.2 ALC Attack Rate .................................................................................................................. 63 DS773F1 CS42L55 5 ...
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... Figure 9.Analog Input Signal Flow ............................................................................................................ 23 Figure 10.Stereo Pseudo-Differential Input ............................................................................................... 24 Figure 11.ALC Operation .......................................................................................................................... 25 Figure 12.DSP Engine Signal Flow ........................................................................................................... 26 Figure 13.Analog Output Stage ................................................................................................................. 27 Figure 14.Adaptive Mode 00 ..................................................................................................................... 28 Figure 15.VHPFILT Transitions ................................................................................................................. 30 Figure 16.VHPFILT Hysteresis ................................................................................................................. 30 Figure 17.Class H Power to Load vs. Power from VCP Supply ................................................................ 31 6 CS42L55 DS773F1 ...
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... Figure 26.HP/Line Output Volume vs. Volume Setting ............................................................................. 69 Figure 27.ADC Passband Ripple .............................................................................................................. 70 Figure 28.ADC Stopband Rejection .......................................................................................................... 70 Figure 29.ADC Transition Band ................................................................................................................ 70 Figure 30.ADC Transition Band Detail ...................................................................................................... 70 Figure 31.DAC Passband Ripple .............................................................................................................. 70 Figure 32.DAC Stopband .......................................................................................................................... 70 Figure 33.DAC Transition Band ................................................................................................................ 70 Figure 34.DAC Transition Band (Detail) .................................................................................................... 70 DS773F1 CS42L55 7 ...
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... Line Audio Output (Output) - The full-scale output level is specified in the Line Output Characteristics LINEOUTB 16 specification table LINEREF 15 Pseudo Diff. Line Output Reference (Input) - Ground reference for the line amplifiers SDA 3 SCL 4 GND/Thermal Pad VCP Top-Down (Through Package) 8 View Pin Description CS42L55 29 28 AIN1REF 27 AIN1A 26 AIN2B 25 AIN2REF 24 AIN2A 23 AFILTB 22 AFILTA FILT DS773F1 ...
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... Weak Pull-up 1 3.3 V, CMOS (~1 MΩ) Weak Pull-up 1 3.3 V, CMOS (~1 MΩ 3.3 V, CMOS - - - - CS42L55 and “Line Power Control” on page 43. “QFN Ther- Receiver 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3 3 3 3 ...
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... AIN2A SCL 1 µF AIN2REF SDA AIN2B Ω AGND VL 0.1 µF AFILTA AFILTB VQ FILT+ GND/Thermal Pad Figure 1. Typical Connection Diagram CS42L55 +1. +2. kΩ 33 Ω Headphone Out Left & Right 33 Ω 3300 pF R ext Line Level Out LPF is Optional * Left & Right * R ext ...
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... DS773F1 Symbol VA VCP VLDO VL T Commercial - CNZ Symbol VA, VCP, VLDO Analog, Charge Pump, LDO VL Serial/Control Port Interface I (Note 2) in (Note (Note 3) IND stg CS42L55 Min Max Units 1.65 2. 1.65 2.71 V 1.65 3.47 V °C -40 +85 A Min Max Units -0.3 3 ...
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... ANALOG INPUT CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L55 are shown in the gram" on page 10; Input kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA; GND = AGND = +25°C; Measurement bandwidth kHz. Sample Frequency = 48 kHz. A Parameter (Note 4) Analog In to ADC (PGA bypassed) ...
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... HPF parameters are for kHz. 9. Characteristics are based on the default setting in register 10. Settling time decreases at higher corner frequency settings. DS773F1 (Note 8) to -0.05 dB corner corner (Note 9) to -3.0 dB corner to -0.05 dB corner “HPF Control (Address 09h)” on page CS42L55 Min Typ Max Unit -0.07 - +0. 0.421 ...
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... HP OUTPUT CHARACTERISTICS Test conditions (unless otherwise specified): Connections to the CS42L55 are shown in the page 10; Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA, VCP Mode; GND = AGND = Measurement bandwidth kHz; Sample Frequency = 48 kHz; Test load Ω, C and test load R = 150 pF for a headphone load. (See ...
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... LINE OUTPUT CHARACTERISTICS Test conditions (unless otherwise specified): Connections to the CS42L55 are shown in the page 10; Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA, VCP Mode; GND = AGND = Measurement bandwidth kHz; Sample Frequency = 48 kHz; Test load R page 15). Parameter (Note 11) ...
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... ANALOG PASSTHROUGH CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L55 are shown in the page 10; Input kHz sine wave through the passive input filter shown in plies = VA, VCP Mode; GND = AGND = kHz. Parameter Analog Amp (ADC is powered down kΩ (+2 dB Output Analog ...
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... SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge Notes: 17. After powering up the CS42L55, RESET should be held low after the power supplies and clocks are settled. This specification is valid with the recommended capacitor on VDFILT. 18. The device will periodically extend the SCLK high time to compensate for the fractional MCLK/SCLK ratio ...
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... Repeated Start t high sud t sust low hdd Figure 7. I²C Control Port Timing CS42L55 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 1000 , of SCL. fc Stop susp ...
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... POWER SUPPLY REJECTION (PSRR) CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L55 are shown in the page 10; GND = AGND = 0 V; all voltages with respect to ground. Parameters PSRR with 100 mVpp, 1 kHz signal (Note 20) PSRR with 100 mVpp signal (Note 20) Notes: 20. Valid with the recommended capacitor values on FILT+ and VQ, no load on HP and Line. Increasing the capacitance on FILT+ and VQ will also increase the PSRR ...
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... CS42L55 Typical Current (mA VCP VA VLDO VL Total Class H Power Mode (mW) page 45 - 0.002 0.003 0.002 0.001 - 0.003 0.002 0.039 0.006 - 0.002 0.005 0.223 0.006 - 0.002 0.002 0.010 0.002 - 0.003 0.859 0.650 0.017 - 0.002 1.053 0.650 0.018 - 0.002 1.116 0.795 0.022 - 0.002 1.470 0.800 0.022 VCP/2 0 ...
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... CS42L55 Typical Current (mA VCP VA VLDO VL Total Class H Power Mode (mW) page 45 - 0.001 0.001 0.001 0.000 0.01 - 0.000 0.000 0.064 0.007 0.18 - 0.000 0.013 0.385 0.007 1.01 - 0.000 0.000 0.018 0.000 0.05 - 0.000 0.752 0.743 0.019 3.79 - 0.000 0.997 0.750 0.019 4. ...
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... Basic Architecture The CS42L55 is a highly integrated, ultra-low power, 24-bit audio CODEC comprised of stereo A/D and D/A converters with pseudo-differential stereo input and output amplifiers. The ADC and DAC are de- signed using multi-bit delta-sigma techniques; both converters operate at a low oversampling ratio of 64xFs, maximizing power savings while maintaining high performance ...
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... NGDELAY[1:0] ALCB ALCBSRDIS ALCBZCDIS Gain Adjust BOOSTB ADCBMUTE HPFRZB DIGSFT HPB ADCBATT[7:0] HPFB_CF[1:0] ADCB=A TO DSP Engine FROM DSP ENGINE Figure 9. Analog Input Signal Flow CS42L55 PDN_ADCA INV_ADCA PDN_CHRG ADC ADCAMUX[1:0] PGAAMUX PDN_ADCA PGAAVOL[5:0] PGAB=A ANLGZC PDN_ADCB PGABVOL[5:0] PGAB=A ANLGZC PGABMUX ADCBMUX[1:0] ...
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... Pseudo-Differential Inputs The CS42L55 implements a pseudo-differential input stage. The AINxREF inputs are intended to be used as a pseudo-differential reference signal. This feature provides 0 noise rejection with single-ended sig- nals. Figure 10 shows a basic diagram outlining the internal implementation of the pseudo-differential in- put stage, including a recommended stereo pseudo-differential input topology. If pseudo-differential input functionality is not required, simply leave the AINxREF pin floating ...
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... Analog In to Analog Out Passthrough The CS42L55 accommodates analog routing of the analog input signal directly to the headphone and line out amplifiers. This feature is useful in applications that utilize an FM tuner where audio recovered over-the- air must be transmitted to the headphone amplifier without digital conversion in the ADC and DAC. This an- alog passthrough path reduces power consumption and is immune to modulator switching noise that could interfere with some tuners ...
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... DIGSFT PLYBCKB=A Beep VOL Generator * MSTxVOL[7:0], MSTxMUTE and DIGSFT are always available regardless of the PDN_DSP setting. Figure 12. DSP Engine Signal Flow “Beep Generator” on page 31 for all referenced controls CS42L55 LIMARATE[7:0] LIMRRATE[7:0] LMAX[2:0] CUSH[2:0] LIMSRDIS LIMIT LIMIT_ALL Limiter Peak Detect Bass/ ...
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... The charge pump receives its input voltage from the voltage present on the VCP pin of the CS42L55. From this input voltage, the charge pump creates the differential rail voltages that are supplied to the amplifier output stages. The charge pump is capable of supplying two sets of differential rail voltages. One set is equal to ± ...
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... Adapted to Volume Settings (Mode 00) When the Adaptive Power bits are set to 00, the CS42L55 decides which set of rail voltages to send to the amplifiers based upon the gain and attenuation levels of all active internal processing blocks. In order to adjust for external analog (line or microphone sources) or digital (DSP) input volume settings, it also takes into account the settings of the AIN and DIN advisory volume registers ...
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... Adapted to Output Signal (Mode 11) When the Adaptive Power bits are set to 11, the CS42L55 decides which of the two sets of rail voltages to send to the amplifiers based solely upon the level of the signal being sent to the amplifiers. If the signal that is sent to the amplifiers would cause the amplifiers to clip when operating on the lower set of rail volt- ages, the control logic instructs the charge pump to provide the higher set of rail voltages (± ...
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... Output Level -10 dB Amplifier Rail Voltage VCP VCP 2 - VCP 2 - VCP 30 Ideal Transition Actual Transition caused by VHPFILT Capacitor Actual Transition caused by VHPFILT Capacitor Ideal Transition Figure 15. VHPFILT Transitions Figure 1 second Figure 16. VHPFILT Hysteresis CS42L55 Time 16. Time Time DS773F1 ...
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... Efficiency As discussed in previous sections, the amplifiers internal to the CS42L55 operate from one of two sets of rail voltages, based upon the needs of the signal being amplified or the total gain/attenuation settings. The power curves for the two modes of operation are shown in plied to a load versus the power drawn from the supply for each of the three use cases. ...
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... Register Location “Limiter Release Rate” on page 62, “Limiter Attack Rate” on page 62 “Limiter Maximum Threshold” on page 60, “Limiter Cushion Threshold” on page 61 “Limiter Soft Ramp Disable” on page 66 “Master Volume Control: MSTA (Address 18h) & MSTB (Address 19h)” on page 57 CS42L55 ... DS773F1 ...
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... Input MAX[2:0] Limiter Volume Output (after Limiter) MAX[2:0] DS773F1 ATTACK/RELEASE SOUND CUSHION ARATE[5:0] RRATE[5:0] Figure 19. Peak Detect & Limiter CS42L55 CUSH[2:0] 33 ...
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... AOUTB / AINxB Figure 20. I²S Format “Register Description” on page CS42L55 01 0x1D 11 0x1B 01 0x19 01 0x15 11 0x13 01 0x11 01 0x0D 11 0x0B 01 0x09 01 0x1D 11 0x1B 01 0x19 01 0x15 11 0x13 01 0x11 01 ...
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... Step 12b,15b ....................... “Headphone Volume Control” on page DS773F1 4.13 “Required Initialization Settings” on page for the required configuration for a given master clock. 57, “Line Channel x Mute” on page 58 57, “Line Volume Control” on page 58 CS42L55 37. 4.8 “Serial Port 4.8 “Serial Port Clock- 35 ...
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... During power down, the CODEC attempts to power down on a zero cross transition of the analog 36 57, “Line Volume Control” on page 58 57, “Line Channel x Mute” on page 58 4.13 “Required Initialization Settings” on page 57, “Line Channel x Mute” on page 58 57, “Line Volume Control” on page 58 CS42L55 37. DS773F1 ...
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... Write 0xF8 to register 0x3A. 10. Write 0xD3 to register 0x3C. 11. Write 0x23 to register 0x3D. 12. Write 0x81 to register 0x3E. 13. Write 0x46 to register 0x3F. 14. Write 0x00 to register 0x00. CS42L55 “Line Channel x Mute” on page 58 Current adjustments are made in the following sections: 1. [Enable test register access.] 2. Digital Regulator. ...
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... SDA while the clock is high. A Stop condition is defined as a rising transition of SDA while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42L55 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). ...
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... The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads. If INCR is set to 1, MAP will auto-in- crement after each byte is read or written, allowing block reads or writes of successive registers. DS773F1 CS42L55 39 ...
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... FREQ1 FREQ0 ONTIME3 OFFTIME0 BPVOL4 BPVOL3 Reserved TREB_CF1 TREB_CF0 TREB1 TREB0 BASS3 MSTAVOL5 MSTAVOL4 MSTAVOL3 MSTBVOL5 MSTBVOL4 MSTBVOL3 HPAVOL5 HPAVOL4 HPAVOL3 CS42L55 REVID2 REVID1 REVID0 PDN PDN_LINA0 MCLKDIV2 MCLKDIS 32kGROUP RATIO1 RATIO0 Reserved Reserved Reserved DIGSFT Reserved FREEZE LINEAMUX HPBMUX HPAMUX ...
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... ALCA ALCARATE5 AALCRATE4 ALCARATE3 ALCARATE2 ALCARATE1 ALCARATE0 ALCRRATE5 ALCRRATE4 ALCRRATE3 ALCRRATE2 ALCRRATE1 ALCRRATE0 ALCMAX0 ALCMIN2 NGBOOST THRESH2 ALCAZCDIS DSPBOVFL DSPAOVFL MIXBOVFL Reserved Reserved CHGFREQ3 CHGFREQ2 CHGFREQ1 CS42L55 HPBVOL3 HPBVOL2 HPBVOL1 LINEAVOL2 LINEAVOL1 AINADV3 AINADV2 AINADV1 DINADV3 DINADV2 DINADV1 CUSH1 CUSH0 Reserved ...
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... All Reserved registers must maintain their default state. I²C Address: 1001010[R/W] 6.1 Fab I.D. and Revision Register (Address 01h) (Read Only Reserved Reserved Reserved 6.1.1 Chip Revision (Read Only) CS42L55 revision level. REVID[2:0] Revision Level 000 A0 001 A1 6.2 Power Control 1 (Address 02h ...
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... Serial Port Clocks 0 Slave (Input ONLY) 1 Master (Output ONLY) Application: “Serial Port Clocking” on page 34 6.4.2 SCLK Polarity Configures the polarity of the SCLK signal. INV_SCLK SCLK Polarity 0 Not Inverted 1 Inverted DS773F1 PDN_HPA0 PDN_LINB1 M/S INV_SCLK SCK=MCK1 CS42L55 PDN_LINB0 PDN_LINA1 PDN_LINA0 SCK=MCK0 MCLKDIV2 MCLKDIS 43 ...
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... Sample Rate Group” on page page 45). Low sample rates may also affect dynamic range performance in the typical audio band. Refer to the referenced application for more information SPEED1 SPEED0 “Master/Slave Mode” on page 45) and the RATIO[1:0] bits CS42L55 32kGROUP RATIO1 RATIO0 43. (“Internal MCLK/LRCK Ratio” on DS773F1 ...
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... H Amplifier” on page 27 6.7 Miscellaneous Control (Address 07h DIGMUX Reserved Reserved 6.7.1 Digital MUX Selects the signal source for the ADC serial port. DIGMUX SDOUT Signal Source 0 ADC 1 DSP Mix DS773F1 ADPTPWR0 Reserved Reserved ANLGZC CS42L55 Reserved Reserved Reserved DIGSFT Reserved FREEZE 45 ...
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... PMIXxMUTE (“PCM Mixer Channel x Mute” on page PMIXxVOL[6:0] (“PCM Mixer Channel x Volume” on page MSTxMUTE (“Master Playback Mute” on page MSTxVOL[7:0] (“Master Volume Control” on page ADCAMUX0 LINEBMUX (“PGA x Input Select” on page CS42L55 49) 57) 57) 58) 58) 48) 50) 51) 51) 52) 52) 51) 57) ...
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... Sets the corner frequency (-3 dB point) for the internal High-Pass Filter (HPF). HPFx_CF[1:0] HPF Corner Frequency Setting (Fs=48 kHz 119 Hz 10 236 Hz 11 464 Hz DS773F1 (“PGA x Input Select” on page (“PGA x Input Select” on page HPFRZA HPFB_CF1 CS42L55 49) to select an input channel. 49) to select an input channel HPFB_CF0 HPFA_CF1 HPFA_CF0 47 ...
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... Configures the polarity of the ADC signal. INV_ADCx ADC Signal Polarity 0 Not Inverted 1 Inverted 6.10.5 ADC Mute Configures a digital mute on ADC channel x. ADCxMUTE ADC Mute 0 Not muted. 1 Muted DIGSUM0 INV_ADCB Serial Output Signal CS42L55 2 1 INV_ADCA ADCBMUTE ADCAMUTE Right Channel ADCB (ADCA + ADCB)/2 (ADCA - ADCB)/2 ADCA DS773F1 0 ...
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... Volume 01 1111 12 dB ... ... 01 1000 12 dB ... ... 00 0001 +0 0000 1111 -0.5 dB ... ... 11 0100 -6.0 dB ... ... 10 0000 -6.0 dB Step Size: 0.5 dB Notes: 1. Refer to Figure 23 and DS773F1 4 3 PGAxVOL4 PGAxVOL3 Figure 24 on page 69 for differential and integral nonlinearity (DNL and INL). CS42L55 PGAxVOL2 PGAxVOL1 PGAxVOL0 49 ...
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... DSP Engine Controls/Blocks AMIXxMUTE (“ADC Mixer Channel x Mute” on page AMIXxVOL[6:0] (“ADC Mixer Channel x Volume” on page PMIXxMUTE (“PCM Mixer Channel x Mute” on page PMIXxVOL[6:0] (“PCM Mixer Channel x Volume” on page Beep Generator, Tone Control, De-Emphasis CS42L55 ADCxATT2 ADCxATT1 ADCxATT0 INV_PCMA ...
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... ADC Mixer Channel x Volume Sets the volume/gain of the ADC mix in the DSP Engine. AMIXxVOL[6:0] Volume 001 1000 +12.0 dB ... ... 000 0001 +0.5 dB 000 0000 0 dB 111 1111 -0.5 dB ... ... 001 1001 -51.5 dB Step Size: 0.5 dB DS773F1 AMIXxVOL4 AMIXxVOL3 CS42L55 AMIXxVOL2 AMIXxVOL1 AMIXxVOL0 51 ...
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... Sets the volume/gain of the PCM mix from the serial data input (SDIN) to the DSP Engine. PMIXxVOL[6:0] Volume 001 1000 +12.0 dB ... ... 000 0001 +0.5 dB 000 0000 0 dB 111 1111 -0.5 dB ... ... 001 1001 -51.5 dB Step Size: 0 PMIXxVOL4 PMIXxVOL3 CS42L55 PMIXxVOL2 PMIXxVOL1 PMIXxVOL0 DS773F1 ...
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... Hz 1111 2130.68 Hz Application: “Beep Generator” on page 31 Notes: 1. This setting must not change when BEEP is enabled. 2. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. DS773F1 FREQ0 ONTIME3 CS42L55 ONTIME2 ONTIME1 ONTIME0 53 ...
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... Application: “Beep Generator” on page 31 Notes: 1. This setting must not change when BEEP and/or REPEAT is enabled. 2. Beep off time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode BPVOL4 BPVOL3 CS42L55 BPVOL2 BPVOL1 BPVOL0 DS773F1 ...
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... Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON for the maximum ONTIME duration. 6.18.2 Treble Corner Frequency Sets the corner frequency for the treble shelving filter. TREBCF[1:0] Treble Corner Frequency Setting 00 5 kHz 01 7 kHz 10 10 kHz 11 15 kHz DS773F1 TREBCF1 TREBCF0 CS42L55 BASSCF1 BASSCF0 TCEN 55 ...
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... Sets the gain of the bass shelving filter. BASS[3:0] Gain Setting 0000 +12.0 dB ··· ··· 0111 +1.5 dB 1000 0 dB 1001 -1.5 dB ··· ··· 1111 -10.5 dB Step Size: 1 TREB0 BASS3 CS42L55 BASS2 BASS1 BASS0 DS773F1 ...
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... Step Size: 1.0 dB Note: 1. The step size may deviate from 1.0 dB. Refer to DS773F1 MSTxVOL4 MSTxVOL3 HPxVOL4 HPxVOL3 (Note (Note Figure 25 CS42L55 2 1 MSTxVOL2 MSTxVOL1 MSTxVOL0 2 1 HPxVOL2 HPxVOL1 HPxVOL0 1)) 1)) and Figure 26 on page 69 ...
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... Step Size: 1.0 dB Note: 1. The step size may deviate from 1.0 dB. Refer LINExVOL4 LINExVOL3 (Note (Note Figure 25 on page 69 CS42L55 2 1 LINExVOL2 LINExVOL1 LINExVOL0 1)) 1)) and Figure 26 on page DS773F1 0 69. ...
Page 59
... Between the headphone and line, the final output voltage from the charge pump is dictated by the highest required advisory volume. When any respective amplifier is powered down, the charge pump’s voltage automatically adjusts to the appropriate level. DS773F1 AINADV4 AINADV3 DINADV4 DINADV3 CS42L55 AINADV2 AINADV1 AINADV0 DINADV2 DINADV1 DINADV0 59 ...
Page 60
... Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack PCMASWP0 ADCBSWP1 CUSH2 CUSH1 62). CS42L55 2 1 ADCBSWP0 ADCASWP1 ADCASWP0 PCM Mix to HP/LINEOUTB Right (Left + Right)/2 Left ADC Mix to HP/LINEOUTB Channel Right (Left + Right)/2 Left ...
Page 61
... Apply the necessary attenuation on BOTH channels when the signal amplitudes on any ONE channel rises 1 above LMAX. Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below CUSH. Application: “Limiter” on page 32 DS773F1 62) until levels lie between the LMAX and CUSH thresholds LIMRRATE4 LIMRRATE3 CS42L55 LIMRRATE2 LIMRRATE1 LIMRRATE0 61 ...
Page 62
... MSTxVOL[7:0] 57) setting. 46) setting unless the disable bit LIMARATE4 LIMARATE3 60). 46) setting unless the disable bit AALCRATE4 ALCARATE3 CS42L55 (“Limiter Soft Ramp Dis LIMARATE2 LIMARATE1 LIMARATE0 (“Limiter Soft Ramp Disable” ALCARATE2 ALCARATE1 ALCARATE0 DS773F1 ...
Page 63
... DIGSFT (“ALCx Soft Ramp Disable” on page ALCRRATE4 ALCRRATE3 61) and returns the signal level to the PGAx- 49) and ADCxVOL[7:0] 46) and ANLGZCx CS42L55 (“Digital Soft Ramp” on page 46) setting or “ALCx Zero Cross Disable” ALCRRATE2 ALCRRATE1 ALCRRATE0 (“ADCx Volume” on page 50) setting. (“ ...
Page 64
... Both channels A & B; Both channels must fall below the threshold setting for the noise gate attenuation to 1 take effect ALCMIN2 ALCMIN1 63). “ALC Release Rate” on page 63) until levels lie between the ALCMAX and AL THRESH2 THRESH1 CS42L55 ALCMIN0 Reserved Reserved THRESH0 NGDELAY1 NGDELAY0 DS773F1 ...
Page 65
... ON; ALC volume changes take effect at any time, regardless of the ANLGZC setting. DS773F1 (“ALCx Soft Ramp Disable” on page ALCAZCDIS LIMSRDIS (“Digital Soft Ramp” on page (“Analog Zero Cross” on page CS42L55 Minimum Setting (NG_BOOST = ‘1’b) -34 dB -36 dB -40 dB -43 dB -46 dB -52 dB -58 dB -64 dB 65) is enabled ...
Page 66
... No digital clipping has occurred in the data path of the ADC and PCM mix of the DSP. 1 Digital clipping has occurred in the data path of the ADC and PCM mix of the DSP. 66 (“Digital Soft Ramp” on page DSPAOVFL MIXBOVFL CS42L55 46) setting MIXAOVFL ADCBOVFL ADCAOVFL DS773F1 ...
Page 67
... Charge Pump Frequency Sets the charge pump frequency on FLYN and FLYP. CHGFREQ[3:0] N 0000 0 ... 0101 5 ... 1111 15 Formula: Frequency = 1.5 MHz/(N+2) Note: The output THD+N performance improves at higher frequencies; power consumption increases at higher frequencies. DS773F1 Reserved CHGFREQ3 CS42L55 CHGFREQ2 CHGFREQ1 CHGFREQ0 67 ...
Page 68
... QFN Thermal Pad The CS42L55 comes in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers ...
Page 69
... PGA Volume Setting Figure 23. PGA Step Size vs. Volume Setting -60 -50 -40 -30 -20 HP/Line Volume Setting Figure 25. HP/Line Step Size vs. Volume Setting DS773F1 - Figure 24. PGA Output Volume vs. Volume Setting 1 0.8 0.6 0.4 0.2 0 -10 0 +10 + Figure 26. HP/Line Output Volume vs. Volume Setting CS42L55 PGA Volume Setting ...
Page 70
... Figure 28. ADC Stopband Rejection 0.58 0.61 0.64 Figure 30. ADC Transition Band Detail 0.3 0.35 0.4 0.45 0.54 0.56 0.58 0.6 Figure 34. DAC Transition Band (Detail) CS42L55 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 0.1 0.2 0.3 ...
Page 71
... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. DS773F1 will effectively move the band-limiting pole of the amp in the L CS42L55 71 ...
Page 72
... JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol 2 Layer Board 4 Layer Board CS42L55 (Note MILLIMETERS NOM MAX - 0.50 - 0.05 0.20 0.25 0.40 REF 5.00 5.05 5.00 5.05 3 ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. DS773F1 Package Pb-Free Grade 36L-QFN YES Commercial - Changes www.cirrus.com/corporate/contacts/sales.cfm CS42L55 Temp Range Container Order # Rail CS42L55-CNZ °C to +85°C Tape & Reel CS42L55-CNZR - - CDB42L55 73 ...