CS4299-JQZ Cirrus Logic Inc, CS4299-JQZ Datasheet
CS4299-JQZ
Specifications of CS4299-JQZ
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CS4299-JQZ Summary of contents
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... AC ’97 interface, implements a cost effective, superior quality, audio solution. The CS4299 surpasses PC 99 and AC ’97 2.1 audio quality standards. ORDERING INFO CS4299-KQZ lead-free CS4299-JQZ lead-free 48-pin LQFP 9x9x1.4 mm ANALOG INPUT MUX AND OUTPUT MIXER SRC PCM_DATA GAIN / MUTE CONTROLS ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com CS4299 CS4299 DS319PP6 ...
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... Figure 2. Codec Ready from Startup or Fault Condition ........................................................... 8 Figure 3. Clocks ........................................................................................................................ 8 Figure 4. Data Setup and Hold.................................................................................................. 9 Figure 5. PR4 Powerdown and Warm Reset ............................................................................ 9 Figure 6. Test Mode .................................................................................................................. 9 Figure 7. AC-link Connections ................................................................................................ 10 Figure 8. Mixer Diagram.......................................................................................................... 12 Figure 9. AC-link Input and Output Framing ........................................................................... 13 Figure 10. Line Input (Replicate for Video and Aux) ...............................................................35 DS319PP6 ........................................................28 CS4299 CS4299 ...
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... Table 4. Analog Mixer Input Gain Values................................................................................24 Table 5. Stereo Volume Register Index ..................................................................................24 Table 6. Input Mux Selection...................................................................................................25 Table 7. Slot Mapping ............................................................................................................29 Table 8. Device ID with Corresponding Part Number .............................................................31 Table 9. Revision Values.........................................................................................................31 Table 10. Powerdown PR Bit Functions..................................................................................33 Table 11. Powerdown PR Function Matrix ..............................................................................34 Table 12. Power Consumption by Powerdown Mode ............................................................. CS4299 CS4299 DS319PP6 ...
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... D-A - -91 -80 A-D - -88 -80 A-D - -84 - -100 730 - 5 2.0 2.28 2.5 refers to the digital output pin loading. DL CS4299 CS4299 = 25° C, ambient =100 kΩ/ AL CS4299-JQZ Min Typ Max Unit - 0.91 1. RMS - 0.91 1. RMS - 0.091 0. RMS 0.91 1.0 1.13 V RMS 20 - 20,000 20,000 20,000 ...
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... AVss2 = DVss1 = DVss2 = 0 V) Symbol +3.3 V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 (AVss = DVss = 0 V) Symbol Min 0.65 x DVdd ih V 0.90 x DVdd 0.99 x DVdd -10 -10 - (Note 4) - CS4299 CS4299 Min Typ Max Unit - Min Typ Max Unit -0 ...
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... isetup T 0 ihold T 2 irise T 2 ifall (Note orise (Note ofall T - s2_pdown T 1.0 sync_pr4 T 162.8 sync2clk 15 setup2rst (Note off CS4299 CS4299 = 25° C, ambient Typ Max Unit µ µs 40.0 - µs 62.5 - µ 12.288 - MHz 81 750 kHz µs 20.8 - µs 1 ...
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... BIT_CLK RESET# Vdd BIT_CLK SYNC CODEC_READY Figure 2. Codec Ready from Startup or Fault Condition BIT_CLK T orise SYNC T irise rst_low T vdd2rst# Figure 1. Power Up Timing T sync2crd clk_high clk_low clk_period T T ifall T sync_high sync_low T sync_period Figure 3. Clocks CS4299 CS4299 T rst2clk T ifall DS319PP6 ...
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... SDATA_OUT Write to 0x20 SDATA_IN SYNC RESET# SDATA_OUT, SYNC SDATA_IN, BIT_CLK DS319PP6 isetup Figure 4. Data Setup and Hold Slot 2 Data PR4 Don’t Care T s2_pdown Figure 5. PR4 Powerdown and Warm Reset T setup2rst T off Figure 6. Test Mode CS4299 CS4299 T ihold T T sync_pr4 sync2clk Hi ...
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... During each au- dio frame, data is passed bi-directionally between the CS4299 and the controller. The input frame is driven from the CS4299 on the SDATA_IN line. The output frame is driven from the controller on the SDATA_OUT line ...
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... In addition, the Intel (ICHx) specification requires support for five more audio rates (8, 11.025, 16, 22.05, and 32). The CS4299 supports all these rate, as shown in Table 7 on page 29. 2.4 Output Mixer The CS4299 has two output mixers, illustrated in Figure 8 ...
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... ANALOG STEREO 3D OUTPUT OUTPUT MIXER MIXER STEREO TO MONO MIXER Σ 1/2 Σ STEREO TO MONO MIXER 1/2 Figure 8. Mixer Diagram CS4299 CS4299 BYPASS BUFFER DAC DIRECT MASTER MODE VOLUME OUTPUT MUTE BUFFER ALT LINE VOLUME OUTPUT MUTE BUFFER MONO OUT ...
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... The first slot, called the tag slot, contains bits indicating if the CS4299 is ready to receive data (input frame) and which, if any, other slots contain valid data. Slots 1 through 12 contain audio or control/status data ...
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... AC-Link Serial Data Output Frame In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4299 from the AC ’97 controller. Figure 9 illustrates the serial port timing. The PCM playback data being passed to the CS4299 is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’ ...
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... See Figure 9 for bit frame positions. RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the CS4299. All registers are defined at word addressable boundaries. The RI0 bit must be ‘clear’ to access CS4299 registers. 3.1.3 Command Data Port (Slot 2) ...
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... AC-Link Audio Input Frame In the serial data input frame, data is passed on the SDATA_IN pin from the CS4299 to the AC ’97 con- troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illus- trates the serial port timing. ...
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... ADC is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and the SM[1:0] and AMAP bits in the AC Mode Control Reg- ister (Index 5Eh). The definition of each slot can be found in Table 8 on page 30. DS319PP6 CS4299 CS4299 Reserved ...
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... SYNC assertion. Upon loss of synchronization with the controller, the CS4299 will ‘clear’ the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the CS4299 will ignore all register reads and writes and will discontinue the transmission of PCM capture data ...
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... DDM AMAP 0 0 Reserved CC6 CC5 CC4 CC3 CC2 CC1 CC0 Table 1. Mixer Registers CS4299 CS4299 Default 0 0 ID4 MR5 MR4 MR3 MR2 MR1 MR0 0 MR5 MR4 MR3 MR2 MR1 MR0 0 MM5 MM4 MM3 MM2 MM1 MM0 0 0 PV3 PV2 PV1 ...
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... The data in this register is read-only data. Any write to this register causes a Register Reset to the default state of the audio (Index 00h - 38h) and vendor spe- cific (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4299. 4.2 ...
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... Write Read Level 000000 000000 0 dB 000001 000001 -1.5 dB … … ... 011111 011111 -46.5 dB 100000 011111 -46.5 dB ... ... ... 111111 011111 -46.5 dB Table 2. Analog Mixer Output Attenuation D10 CS4299 CS4299 MR5 MR4 MR3 MR2 MR1 MM5 MM4 MM3 MM2 MM1 D0 MR0 D0 MM0 21 21 ...
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... Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is + -34.5 dB gain. See Table 4 on page 24 for further details. Default 8008h. This value corresponds gain and Mute ‘set’ D10 D10 CS4299 CS4299 PV3 PV2 PV1 PV0 GN4 GN3 GN2 GN1 DS319PP6 GN0 ...
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... Gain Level GN[4:0] 20dB = 0 20dB = 1 00000 +12.0 dB +32.0 dB 00001 +10.5 dB +30.5 dB … … ... 00111 +1.5 dB +21.5 dB 01000 0.0 dB +20.0 dB 01001 -1.5 dB +18.5 dB … … ... 11111 -34.5 dB -14.5 dB Table 3. Microphone Input Gain Values CS4299 CS4299 GN4 GN3 GN2 GN1 D0 GN0 23 23 ...
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... Table 4. Analog Mixer Input Gain Values Register Index Function 10h Line In Volume 12h CD Volume 14h Video Volume 16h Aux Volume 18h PCM Out Volume Table 5. Stereo Volume Register Index CS4299 CS4299 GR4 GR3 GR2 GR1 DS319PP6 D0 GR0 ...
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... Mic 001 CD Input 010 Video Input 011 Aux Input 100 Line Input 101 Stereo Mix 110 Mono Mix 111 Phone Input Table 6. Input Mux Selection D10 GL2 GL1 GL0 0 0 CS4299 CS4299 SR2 SR1 GR3 GR2 GR1 D0 SR0 D0 GR0 25 25 ...
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... S[3:0] = 1111, the maximum amount of spatial enhancement is added. The 3D function is en- abled and disabled by the 3D bit in the General Purpose Register (Index 20h). Default 0000h. This value corresponds to minimum spatial enhancement added to the output signal D10 MIX MS LPBK 0 D10 CS4299 CS4299 stereo enhancement. This DS319PP6 ...
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... The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec- tion of the CS4299 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 5, Power Management, for more information on the powerdown functions ...
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... PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at ‘0’. Default 0000h 28 28 D10 AMAP D10 CS4299 CS4299 DS319PP6 D0 VRA D0 VRA ...
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... Decode Range 8,000 1F40 11,025 2B11 16,000 3E80 22,050 5622 32,000 7D00 44,100 AC44 48,000 BB80 Bh, Ch, Dh, Eh Table 7. Standard Sample Rates D10 SR9 SR8 SR7 SR6 CS4299 CS4299 SR5 SR4 SR3 SR2 SR1 SR5 SR4 SR3 SR2 SR1 D0 SR0 D0 ...
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... Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit is ‘set’, the CS4299 will mute all analog outputs for the duration of loss of SYNC. If this bit is ‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4299 ex- pects to sample SYNC ‘ ...
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... When ‘set’, the sampling frequency is 44.1 kHz. The actual rate at which S/PDIF data are being transmitted solely depends on the master clock frequency of the CS4299. The Fs bit is merely an indicator to the S/PDIF receiver. L Generation Status. The L bit is mapped to bit 15 of the channel status block. For category codes 001xxxx, 0111xxx and 100xxxx, a value of ‘ ...
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... Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII ‘Y’ character. DID[2:0] Device ID. With a value of DID[2:0] = 011, these bits specify the audio codec is a CS4299. REV[2:0] Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is ‘A’. ...
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... This is done in accordance with the minimum timing specifications in the AC ’97 Seri- al Port Timing section on page 7. Once deasserted, all of the CS4299 registers will be reset to their de- fault power-on states and the BIT_CLK and SDATA_IN signals will be reactivated. DS319PP6 5.1.2 Warm AC ’ ...
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... The PR[6:0] bits in this register control the internal powerdown states of the CS4299. Power- down control is available for individual subsections of the CS4299 by asserting any PRx bit or any com- bination of PRx bits. Most powerdown states can be resumed by clearing the corresponding PRx bit. ...
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... I + DVdd/Rload/2 DVdd CS4299 CS4299 AC Internal Link Clock Off • • • • • (mA) I (mA) AVdd 37.9 37.9 37.9 29.0 31.3 10.7 45 µA 37.9 45 µ ...
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... Figure 10 shows circuitry for a line-level stereo in- put. Replicate this circuit for the Line, Video and Aux inputs. This design attenuates the input by 6 dB, bringing the signal from the PC 99 specified the CS4299 maximum allowed 1 V RMS 6.1.2 CD Input The CD line-level input has an extra pin, CD_GND, providing a pseudo-differential input for both CD_L and CD_R ...
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... The design also sup- ports the recommended advanced frequency re- sponse for voice recognition as specified in PC 99. Note the microphone input to the CS4299 has an integrated pre-amplifier. Using the 20dB bit in the Microphone Volume Register (Index 0Eh) the pre-amplifier gain can be set dB. ...
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... Figure 16 shows a design for a modem connection where the output is fed from the CS4299 MONO_OUT pin through a divider. The divider ratio shown does not attenuate the signal, providing an output voltage output voltage is desired, the resistors can be re- placed with appropriate values, as long as the total load on the output is kept greater than 10 kΩ ...
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... The analog power pins, AVdd1 and AVdd2, supply power to all the analog circuitry on the CS4299. The +5 V analog supply should be generated from a linear voltage regulator (7805 type) connected to a +12 V supply. This helps iso- late the analog circuitry from noise typically found digital supplies ...
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... CS4299 ground potential and de- grading performance. The digital ground pins should be connected to the digital ground plane and kept separate from the analog ground connections of the CS4299 and any other external analog cir- R S/PDIF_OUT 1 SPDO/SDO2 DVdd 3 ...
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... REFFLT AVdd2 Via to Analog Ground Digital Ground Via to Digital Ground Pin 1 0.1 µF DVss1 Y5V 0.1 µF DVss2 Y5V Figure 21. Conceptual Layout for the CS4299 CS4299 CS4299 Via to +5VA 1 µF 0.1 µF Y5V AVss1 AVdd1 Via to Analog Ground Analog Ground DVdd2 Via to +5VD or +3 ...
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... PIN DESCRIPTIONS DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP Figure 22. Pin Locations for the CS4299 CS4299 CS4299 LINE_OUT_R 36 LINE_OUT_L 35 FLTO 34 FLTI 33 FLT3D 32 BPCFG 31 AFLT2 30 AFLT1 29 Vrefout 28 REFFLT 27 AVss1 26 AVdd1 25 DS319PP6 ...
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... AC-coupled, with separate AC-coupling caps, to analog ground. CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20 These inputs form a stereo input pair to the CS4299 intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. ...
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... RESET#. These pins are internally pulled up to the digital supply voltage and should be left floating for logic ‘0’ or tied to digital ground for logic ‘1’. When both pins are left floating the CS4299 is the primary codec. If either or both pins are tied to ground the CS4299 is a secondary codec. ...
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... Analog Reference, Filters, and Configuration REFFLT - Internal Reference Voltage, Input, Pin 27 This signal is the voltage reference used internal to the CS4299. A 0.1 µF and a 1.0 µF (must not be larger than 1 µF) capacitor with short, wide traces must be connected to this pin. No other connections should be made to this pin ...
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... Power Supplies DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9 Digital supply voltage for the AC-link section of the CS4299. These pins can be tied digital or to +3.3 V digital. The CS4299 and controller AC-link should share a common digital supply DVss1, DVss2 - Digital Ground, Pins 4 and 7 Digital ground connection for the AC-link section of the CS4299 ...
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... AC ’97 Registers or Codec Registers Refers to the 64-field register map defined in the AC ’97 Specification. ADC Refers to a single Analog-to-Digital converter in the CS4299. “ADCs” refers to the stereo pair of Analog-to-Digital converters. The CS4299 ADCs have 18-bit resolution. Codec Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the CS4299 ...
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... SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS4299 operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 kHz. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level ...
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... REFERENCE DESIGN GND 2 DS319PP6 + + AVdd2 AVdd1 AVss2 AVss1 XTL_OUT XTL_IN DVdd2 FLTO DVdd1 FLTI CS4299 CS4299 ...
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... Version 6.0, February 1998 3) Cirrus Logic, AN22: Overview of Digital Audio Interface Data Structures, Version 2.0, February 1998 4) Cirrus Logic, AN134: AES and S/PDIF Recommended Transformers, Version 2, April 1999 5) Cirrus Logic, AN165: CS4297A/CS4299 EMI Reduction Techniques, Version 1.0, September 1999 ® 6) Intel , Audio Codec ’ ...
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... CS4299 CS4299 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7 ...
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