AD1836AASZ Analog Devices Inc, AD1836AASZ Datasheet - Page 18

• Manufacturer Part Number: AD1836AASZ
• Description: IC CODEC 4ADC/6DAC 24 BIT 52MQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of AD1836AASZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 6
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 105 / 108
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-BQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 4
• No. Of Dacs: 6
• No. Of Input Channels: 4
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 108dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD1836AZ-DBRD - BOARD EVAL FOR AD1836AAD1836A-DBRD - BOARD EVAL FOR AD1836A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD1836A
Table 11. Pin Function Changes in AUX Mode
Pin Name (I
ASDATA1(O)
ASDATA2(O)/DAUXDATA(O)
DSDATA1(I)
DSDATA2(I)/AAUXDATA(I)
DSDATA3(I)/AAUXDATA2(I)
ALRCLK(O)
ABCLK(O)
DLRCLK(I)/AUXLRCLK(I/O)
DBCLK(I)/AUXBCLK(I/O)
FROM SHARC
FROM EXT A/D
FROM EXT A/D
DLRCLK/AUXLRCLK
DBCLK/AUXBCLK
2
DSDATA3/AUXDATA2
S/AUX Mode)
DSDATA2/AUXDATA1
DSDATA1
MASTER/SLAVE MODE,
FROM ADC SPI PORT
TIMING GEN
LRCLK BCLK
MCLK
I
2
I
I
I
I
I
I
LRCLK for Internal ADC1, ADC2
BCLK for Internal ADC1, ADC2
LRCLK In/Out Internal DACs
BCLK In/Out Internal DACs
2
2
2
2
2
S
2
S Data Out, Internal ADC1
S Data Out, Internal ADC2
S Data In, Internal DAC1
S Data In, Internal DAC2
S Data In, Internal DAC3
S Mode
Figure 12. Extended TDM Mode (Internal Flow Diagram)
DSDATA1
DSDATA2
DSDATA3
LRCLK
BCLK
AUXBCLK
AUXLRCLK
AUXDATA2
AUXDATA1
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DECODE
ADC
I
INDICATES MUX POSITION FOR AUX-TDM MODE
2
AUX Mode
TDM Data Out, to SHARC
AUX—I
TDM Data In, from SHARC
AUX—I
AUX—I
TDM Frame Sync Out, to SHARC
TDM BCKL Out, to SHARC
AUX LRCLK In/Out, Driven by External IRCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/512.
AUX BCLK In/Out, Driven by External BCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/8.
S
MUX
MUX
2
2
2
4 ADC
S Data Out (to External DAC)
S Data In 1 (to External ADC)
S Data In 2 (to External ADC)
SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO
RESET INTERNAL ADC COUNTER
SYNC
S
AUXLRCLK
SPORT
DAC
AUXDATA
ASDATA1
SPORT
I
2
S FORMATTER
AUXBCLK
CHANNELS
ASDATA1
6 MAIN
ABCLK
LRCLK
MUX
2 AUX
CHANNELS
6-CH
DAC
DATA TO SHARC
ALRCLK
ABCLK
ASDATA1
ASDATA2/DAUXDATA
DATA TO EXT DAC
BCLK AND LRCLK FOR
EXT DAC COMES FROM
ADC BCLK, LRCLK.
MUST BE IN I
2
S MODE.