CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet
CS4270-DZZ
Specifications of CS4270-DZZ
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CS4270-DZZ Summary of contents
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... High-Pass Digital Filter 2 Filters This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) CS4270 Analog Supply 3 Internal Voltage Reference External Mute Mute Signals Control 2 ...
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... A used in a wide variety of applications where one audio channel and one DC measurement channel is desired. The CS4270 is available in a 24-pin TSSOP package in both Commercial (-10° to +70° C) and Automotive grades (-40° to +85° C). The CDB4270 Customer Dem- onstration board is also available for device evaluation and implementation suggestions. Please refer to “ ...
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... Output Connections ............................................................................................................... 30 5.5 Mute Control .................................................................................................................................. 30 5.6 Synchronization of Multiple Devices .............................................................................................. 31 5.7 Grounding and Power Supply Decoupling .................................................................................... 31 6. CONTROL PORT INTERFACE ............................................................................................................ 32 6.1 SPI™ Mode ................................................................................................................................... 32 ® 6.2 I²C Mode ...................................................................................................................................... 33 7. REGISTER QUICK REFERENCE ........................................................................................................ 34 8. REGISTER DESCRIPTION .................................................................................................................. 35 8.1 Chip ID - Address 01h ................................................................................................................... 35 DS686PP1 CS4270 3 ...
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... Figure 12. I²C Mode Control Port Timing .................................................................................................. 20 Figure 13. SPI Control Port Timing ........................................................................................................... 21 Figure 14. De-Emphasis Curve ................................................................................................................. 27 Figure 15. CS4270 Recommended Analog Input Network ....................................................................... 28 Figure 16. A/D THD+N Performance vrs. Input Source Resistance ......................................................... 28 Figure 17. A/D Dynamic Range vrs. Input Source Resistance ................................................................. 29 Figure 18. CS4270 Example Analog Input Network .................................................................................. 30 4 CS4270 DS686PP1 ...
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... Figure 19. CS4270 Recommended Analog Output Filter .......................................................................... 30 Figure 20. Suggested Active-Low Mute Circuit ......................................................................................... 31 Figure 21. Control Port Timing, SPI Mode ................................................................................................ 32 Figure 22. Control Port Timing, I²C Mode ................................................................................................. 33 Figure 23. De-Emphasis Curve ................................................................................................................. 39 Figure 24. DAC Single-Speed Stopband Rejection .................................................................................. 41 Figure 25. DAC Single-Speed Transition Band ......................................................................................... 41 Figure 26. DAC Single-Speed Transition Band (detail) ............................................................................. 41 Figure 27 ...
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... Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Character- AOUTB 23 istics specification table Pin Description ® Mode. CS4270 MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST AD2 ® Mode. CDOUT is the output data line for DS686PP1 ...
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... AOUTA Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris- AOUTB 23 tics specification table. DS686PP1 VLC Pin Description CS4270 MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST MDIV2 I²S format for the Serial Audio 7 ...
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... SCL / CCLK (M0) MUTEA RST AOUTA AOUTB MUTEB VLC DGND 2. Use a 47 kΩ pull-down to select Slave Mode or 47 kΩ pull- select Master Mode. See "Master/Slave Mode Selection." Figure 1. CS4270 Typical Connection Diagram CS4270 +3 +3 GND kΩ ( Audio Data Processor SDIN Timing Logic SCLK & ...
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... Control Port Interface V IND-C Digital Interface V IND stg Symbol (Note 3) θ (Multi-layer PCB) TSSOP JA-M θ (Single-layer PCB) TSSOP JA-S CS4270 Specified Operating Conditions. Typical Min Nom Max 3.1 5.0 5.25 3.1 3.3 5.25 1.7 3.3 5.25 -10 - +70 -40 - +85 Min Typ Max -0 ...
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... Fs = 48/96/192 kHz; Test load Min Typ Max 95 105 A-weighted unweighted 92 102 A-weighted 86 96 unweighted - -76 -66 - -36 - -87 -77 - -67 -57 - -27 -17 CS4270 = 3 kΩ 3.3 V Min Typ Max Unit - 97 103 - - 94 100 - - -89 -83 - -76 -70 - -36 -30 - -87 -81 - -67 -61 - -27 - kΩ 3.3 V Min ...
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... Output Impedance of AOUTA and AOUTB 3.3 µF AOUTx AGND Figure 2. Output Test Load DS686PP1 Symbol (1 kHz) I OUTmax OUT 125 100 V out 2.5 3 CS4270 Min Typ Max - 100 - - 0.1 0.25 -100 +100 0.6•VA 0.65•VA 0.7• 100 - - 100 - Safe Operating Region 5 ...
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... Min to -0.1 dB corner corner 0 -.175 .5465 50 (Note 7) tgd - kHz - Fs = 44.1 kHz - kHz - to -0.1 dB corner corner 0 -.15 .5770 (Note 7) 55 tgd - to -0.1 dB corner corner 0 -.12 0.7 51 (Note 7) tgd - Section 9. “Filter Plots” on page CS4270 Typ Max Unit - . .4992 10/ +1.5/+ +.05/-. -.2/-. . .501 ...
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... A-weighted 99 105 unweighted 96 102 (Note 9) THD -95 - -82 - -42 - kHz A-weighted 99 105 unweighted 96 102 - (Note 9) THD -95 - -82 - - A-weighted 99 105 unweighted 96 102 - (Note 9) THD -82 - - Min - - -3 - 0.53*VA - CS4270 Figure 18 input circuit, 1 kHz sine wave in 3.3 V Max Min Typ Max - 96 102 - - -90 - - 102 - - -90 - - 102 - - ...
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... Typ A-weighted 97 105 unweighted 94 102 (Note 10) THD - - kHz A-weighted 97 105 unweighted 94 102 - (Note 10) THD - - A-weighted 97 105 unweighted 94 102 - (Note 10) THD - - Min - - -3 - 0.53*VA - CS4270 Figure 18 input circuit, 1 kHz sine wave in 3.3 V Max Min Typ Max - 94 102 - - -95 -90 - -92 -87 - - 102 - - -95 -90 - -92 -87 - - ...
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... The filter frequency response scales precisely with Fs. 13. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DS686PP1 (Note 11) Symbol (Note 12) (Note 12 (Note 12) (Note 12 (Note 12) (Note 12 (Note 13) (Note 13) Section 9. “Filter Plots” on page 41. See CS4270 Min Typ Max Unit 0.035 dB 0. ...
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... Min 3 VD, VLC = VD, VLC = 3 VD, VLC = Normal Operation - Normal Operation - (Note 14) - (Note 15) PSRR VQ FILT+ Symbol Serial Port V IH Control Port Serial Port V IL Control Port Serial Port V OH Control Port MUTEA, MUTEB CS4270 Typ Max - 1. 0. 221 296 - 255 - - 9.8 323 - VA ...
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... Mode f mclk Control Port Mode f mclk t sclkw t mslr t sdo t sdis t sdih Single-Speed Mode t sclkw Double-Speed Mode t sclkw Quad-Speed Mode t sclkw t slrd t stp t hld t sdis t sdih Table 12. 5 and 7. CS4270 Min Typ Max 108 100 - 216 1.024 - 55.296 1.024 - 55.296 ----------------- - ( ) - ...
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... MSB-1 MSB-2 MSB-3 SDOUT Figure 5. Slave Mode, Left-Justified SAI LRCK input SCLK input t sdo SDOUT MSB-1 MSB-2 MSB-3 t sclkw t sdis CS4270 t slrd t sclkh t sclkl t stp t hld MSB t slrd t sclkh t sclkl t stp t hld Figure 7. Slave Mode, I²S SAI t sdih DS686PP1 MSB-1 MSB ...
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... Figure 11. Format 2, Right-Justified 16-Bit Data. (Available in Control Port Mode only) Format 3, Right-Justified 24-Bit Data. (Available in Control Port Mode only) DS686PP1 + LSB MSB + LSB MSB - I²S Figure 10. Format 24-Bit Data - LSB CS4270 Right Channel + LSB Right Channel + LSB Channel B - Right Right Channel - MSB -6 LSB 19 ...
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... Repeated t high sud t sust low hdd Figure 12. I²C Mode Control Port Timing Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - Stop Start susp hdst t r CS4270 Unit kHz ns µs µs µs µs µs µs ns µs ns µs DS686PP1 ...
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... CONTROL PORT Symbol f sclk t srs (Note 20) t spi t csh t css t scl t sch t dsu (Note 21 (Note 22 (Note 22 srs t spi t css t scl t sch dsu t dh Figure 13. SPI Control Port Timing CS4270 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...
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... Master Mode may be accessed by placing a 47 kΩ pull- the SDOUT (M/S) pin. Configuration of clock ratios in each of these modes is outlined in 5.1.3 System Clocking The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in . ...
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... The operational amplifiers in the input circuitry driving the CS4270 may generate a small DC offset into the ADC. The CS4270 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system ...
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... It is recommended that SCLK be 48x or 64x Fs to maximize system performance. Configuration of clock ratios in each of these modes will be outlined in the In Control Port Mode the CS4270 will default to Slave Mode. The user may change this default setting by changing the status of the M/S bits in the Functional Control Register (03h). ...
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... System Clocking The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in 5.2.4 Clock Ratio Selection In Control Port Master Mode, the user must configure the mode bits (MCLK Freq<2:0>) to set the speed mode and select the appropriate clock ratios ...
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... ADC is routed to the input of the DAC. This mode may be activated by setting the Digital Loopback bit in the ADC & DAC Ctrl register (04h). When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270. Any changes made to the DAC_DIF(4:3) bits while the Digital Loopback bit is set will have no impact on operation until the Digital Loopback bit is released, at which time the Digital Interface Format of the DAC will operate according to the format selected in the DAC_DIF(4:3) bits ...
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... One de-emphasis mode is available via the Control Port and is optimized for 44.1 kHz sampling rate. 5.2.9 Oversampling Modes The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selec- tion is determined by the FM_&_M/S_Mode[1:0] bits in the Functional Mode register (03h). Single-Speed Mode supports input sample rates kHz and uses a 128x oversampling ratio ...
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... Analog Input R1 Figure 15. CS4270 Recommended Analog Input Network Three parameters determine the values of resistors R1 and R2 as shown in attenuation, and input impedance. Source Impedance: Source impedance is defined as the impedance as seen from the ADC looking back into the signal network. The ADC achieves optimal THD+N performance when source impedance is min- imized and THD+N degrades for source impedance greater than 1 kΩ ...
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... Vrms, to the full-scale input of the ADC, 1 Vrms when and is the maximum source impedance for the ADC specifications listed in this Data Sheet. DS686PP1 Source Impedance ( × ------------------------ - R1 + Attenuation Factor ( R2 ------------------------ - ( Input Impedance R1 + Table 6. Analog Input Design Parameters CS4270 ) ...
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... Figure 18. CS4270 Example Analog Input Network 5.4.2 Output Connections The analog output filter present in the CS4270 is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in recommended external analog circuitry is shown in 3.3 µ ...
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... MCLK and LRCK must be the same for all of the CS4270’s in the sys- tem. If only one MCLK source is needed, one solution is to place one CS4270 in Master Mode, and slave all of the other CS4270’s to the one master. If multiple MCLK sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS4270 reset with the inactive edge of MCLK ...
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... SPI™ Mode In SPI Mode the CS4270 chip select signal, CCLK is the Control Port bit clock, CDIN is the input data line from the microcontroller and the chip address is 1001111. All control signals are inputs and data is clocked in on the rising edge of CCLK. ...
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... MAP will be output after the chip address. The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers ...
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... DAC_DIF0 Loopback Invert ADC Invert ADC zc_dac Mute ADC Mute ADC dacA dacA dacA vol<5> vol<4> vol<3> dacB dacB dacB vol<5> vol<4> vol<3> CS4270 rev<2> rev<1> Reserved PDN_DAC MCLK MCLK PopGuard freq<1> freq<0> Reserved Reserved ADC_DIF0 Invert DAC Invert DAC Mute ...
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... The DAC portion of the device will enter a low-power state whenever this bit is set. 8.2.4 Power Down (Bit 0) Function: The device will enter a low-power state whenever this bit is set. The contents of the control registers are retained when the device is in power-down. DS686PP1 id<0> rev<3> Reserved Reserved CS4270 rev<2> rev<1> rev<0> Reserved PDN_DAC PDN 35 ...
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... Reserved Reserved Mode1 8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) Function: In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Control Port Slave Mode, the CS4270 auto-detects speed mode. FM_&_M/S_ FM_&_M/S_ Mode1 ...
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... Left-Justified 24-bit data (default) I² 24-bit data Right-Justified, 16-bit Data Right-Justified, 24-bit Data Table 10. DAC Digital Interface Formats Table 11 and may be seen in Description I² 24-bit data Table 11. ADC Digital Interface Formats CS4270 Section 5.2.7 “High- Table 10 and Figures 9 through 11. Format Figure 0 9 ...
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... ADC ch B ADC ch A 36. Table 9 on page ZeroCross Mode 0 Changes to affect immediately 1 Zero Cross enabled 0 Soft Ramp enabled 1 Soft Ramp and Zero Cross enabled (default) CS4270 invert invert De-emph DAC ch B DAC ch A 36. DS686PP1 ...
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... When this bit is set, the output of the DAC for the selected channel will be muted. DS686PP1 Gain dB T1=50 µs 0dB -10dB F1 F2 3.183 kHz 10.61 kHz Figure 23. De-Emphasis Curve Mute ADC SP Mute ADC Section 5.2.6 “Auto-Mute” on page CS4270 Figure µs Frequency 2 1 Mute DAC SP Mute DAC SP mute polarity 26. shows 0 39 ...
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... Section 8.5.2). Volume Setting 0 dB -0.5 dB -20 dB -20.5 dB -127 dB -127.5 dB Table 13. Digital Volume Control CS4270 2 1 dacA dacA vol<2> vol<1> 08h dacB dacB vol<2> vol<1> DS686PP1 0 dacA vol<0> 0 dacB vol<0> ...
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... Figure 28. DAC Double-Speed Stopband Rejection DS686PP1 Figure 25. DAC Single-Speed Transition Band 0.05 0 -0.05 -0. 1 -0.15 -0. 2 -0.25 0 0.05 0.52 0.53 0.54 0.5 5 Figure 27. DAC Single-Speed Passband Ripple Figure 29. DAC Double-Speed Transition Band CS4270 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs) 41 ...
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... Figure 33. DAC Quad-Speed Transition Band 0 - -1. 5 0.65 0.7 0 Figure 35. DAC Quad-Speed Passband Ripple CS4270 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (normalized to Fs) 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Frequency(normalized to Fs) ...
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... Figure 41. ADC Double-Speed Stopband (detail) CS4270 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (norm alized to Fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (norm alized to Fs) 0 ...
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... Figure 47. ADC Quad-Speed Passband Ripple CS4270 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Frequency (norm alized to Fs) ...
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... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS686PP1 CS4270 45 ...
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... BSC 0.25610 6.30 0.17730 4. 0.02955 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS4270 1 E1 ∝ END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 1.00 1.05 0.245 0.30 2,3 7.80 BSC 7.90 BSC 1 6 ...
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... CS4270 Evaluation Board 13.REVISION HISTORY Release A1 Initial Release DS686PP1 Package Pb-Free Grade 24-TSSOP YES Commercial -10° to +70° C 24-TSSOP YES Automotive -40° to +85° Changes CS4270 Temp Range Container Order # Rail CS4270-CZZ Tape & Reel CS4270-CZZR Rail CS4270-DZZ Tape & Reel CS4270-DZZR - - CDB4270 47 ...
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... Connections” on page 28 that describes A/D input attenuator (resistor Section 10 Section 9 and updated all plots Section 11 and updated dimensions data CS4270 Figure 18 and “single ended output” to Table on page 9 “DAC Analog Characteristics - all Modes” “ADC Analog Characteristics - “ADC Analog Characteristics - “ ...
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... Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS686PP1 www.cirrus.com. CS4270 49 ...