MAX9860ETG+ Maxim Integrated Products, MAX9860ETG+ Datasheet - Page 17

IC CODEC MONO AUD 16BIT 24TQFN

MAX9860ETG+

Manufacturer Part Number
MAX9860ETG+
Description
IC CODEC MONO AUD 16BIT 24TQFN
Manufacturer
Maxim Integrated Products
Type
Audio Codecr
Datasheet

Specifications of MAX9860ETG+

Data Interface
Serial
Resolution (bits)
16 b
Number Of Adcs / Dacs
1 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
81 / 90
Voltage - Supply, Analog
1.7 V ~ 1.9 V
Voltage - Supply, Digital
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX9860 can work with a master clock (MCLK)
supplied from any system clock within the range of
10MHz to 60MHz. Internally, the MAX9860 requires a
10MHz to 20MHz clock so a prescaler divides by 1, 2,
or 4 to create the internal clock (PCLK). PCLK is used
to clock all portions of the MAX9860.
The MAX9860 is capable of supporting any sample rate
from 8kHz to 48kHz, including all common sample rates
(8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz). To
accommodate a wide range of system architectures,
the MAX9860 supports three main clocking modes:
Normal Mode: This mode uses a 15-bit clock divider
coefficient to set the sample rate relative to the
Table 3. Clock Control Registers
REGISTER ADDRESS
PSCLK[1:0]
FREQ[1:0]
16KHZ
BITS
0x03
0x04
0x05
______________________________________________________________________________________
MCLK Prescaler
Divides MCLK down to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz.
10 = Select if MCLK is between 20MHz and 40MHz.
11 = Select if MCLK is greater than 40MHz.
Integer Clock Mode
Enables exact integer mode for three predefined PCLK frequencies. Exact integer mode is normally
intended for master mode, but can be enabled in slave mode if the externally supplied LRCLK exactly
matches the frequency specified in each mode.
00 = Normal operation (configure clocking with the PLL, NHI, and NLO bits).
01 = Select when PCLK is 12MHz (LRCLK = PCLK/1500 or PCLK/750).
10 = Select when PCLK is 13MHz (LRCLK = PCLK/1625 or PCLK/812.5).
11 = Select when PCLK is 19.2MHz (LRCLK = PCLK/2400 or PCLK/1200).
When FREQ ≠ 00, the PLL, NHI, and NLO bits are unused.
16kHz Mode
When FREQ ≠ 00:
0 = LRCLK is exactly 8kHz.
1 = LRCLK is exactly 16kHz.
When FREQ = 00, 16KHZ is used to set the AGC clock rate:
0 = Use when LRCLK ≤ 24kHz.
1 = Use when LRCLK > 24kHz.
PLL
B7
0
Clock Control
16-Bit Mono Audio Voice Codec
B6
0
B5
PSCLK
prescaled MCLK input (PCLK). This allows high flexibili-
ty in both the MCLK and LRCLK frequencies and can
be used in either master or slave mode.
Exact Integer Mode: Common MCLK frequencies
(12MHz, 13MHz, and 19.2MHz) can be programmed to
operate in exact integer mode for both 8kHz and 16kHz
sample rates. In these modes, the MCLK and LRCLK
rates are selected by using the FREQ and 16KHZ bits
instead of the NHI, NLO, and PLL control bits.
PLL Mode: When operating in slave mode, a PLL can
be enabled to lock onto externally generated LRCLK
signals that are asynchronously related to PCLK.
B4
FUNCTION
NLO
NHI
B3
0
B2
FREQ
B1
16KHZ
B0
17

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